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DP83924 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DP83924
Beschreibung Quad 10 Mb/s Ethernet Physical Layer - 4TPHY
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 30 Seiten
DP83924 Datasheet, Funktion
October 1998
DP83924BVCE
Quad 10 Mb/s Ethernet Physical Layer - 4TPHY™
General Description
The DP83924B Quad 10Mbps Ethernet Physical Layer
(4TPHY) is a 4-Port Twisted Pair PHYsical Layer Trans-
ceiver that includes all the circuitry required to interface
four Ethernet Media Access Controllers (MACs) to
10BASE-T. This device is ideally suited for switch hub
applications where 8 to 32 ports are commonly used.
The 4TPHY has three dedicated 10Base-T ports. There is
an additional port that is selectable for either 10Base-T or
for an Attachment Unit Interface (AUI). In 10Base-T mode,
any port can be configured to be Half or Full Duplex.
(Continued)
Features
s 100 pin package
s 10BASE-T and AUI interfaces
s Automatic or manual selection of twisted pair or Attach-
ment Unit Interfaces on port 1
s Direct Interface to NRZ Compatible controllers
s IEEE 802.3u Auto-Negotiation between 10Mb/s Full
and Half Duplex data traffic and parallel detection
s MII-like Serial management interface for configuration
and monitoring of ENDEC/Transceiver operation.
s Programmable MAC Interface supports most
standard 7 signal MAC interfaces
s Twisted Pair Transceiver Module
– On-chip filters for transmit outputs
– Low Power Driver
– Heartbeat and Jabber Timers
– Link Disable and Smart Receive Squelch
– Polarity detection and correction
– Jabber Enable/Disable
– Isolate mode for diagnostics
– Low Power Class AB Attachment Unit Interface (AUI)
Driver for one port
– Enhanced Supply Rejection
– Enhanced Jitter Performance
– Diagnostic Endec Loopback
– Squelch on Collision and Receive Pair
s Serial LED interface for LINK, POLARITY, ACTIVITY,
and ERROR.
s JTAG Boundary Scan per IEEE 1149.1
System Diagram
MAC Serial
NRZ Interface
10BASE-T
10BASE-2
TPI
ports 1-4
DP83924B
AUI
(port 1 option)
RXD4,RXC4,COL4,CRS4
TXD4,TXE4
RXD3,RXC3,COL3,CRS3
TXD3,TXE3
RXD2,RXC2,COL2,CRS2
TXD2,TXE2
RXD1,RXC1,COL1,CRS1
TXD1,TXE1
TXC
MDIO MDC
Serial Mgmt Interface
4TPHY™ is a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
MAC
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DP83924 Datasheet, Funktion
1.0 Pin Information (Continued)
Table 1. NRZ CONTROLLER INTERFACE and MANAGEMENT INTERFACE.
These pins provide the interface signalling between the Media Access Controller and the transceiver. (30 Pins)
Symbol Pin # Type
Description
MDIO
94 I/O Management Data I/O: When management interface is enabled (strap option,
LINK_4
COL[2]=1), this Bidirectional signal transfers data on the management interface be-
tween the controller and the transceiver.
Link Lost Status Port 4: When “Disable Management Interface” mode is selected,
(strap option, COL[2]=0), this pin outputs the link lost status for port 4. If link is lost, this
output is high.
INT 92 OD Interrupt: When “Enable Management Interface” mode is selected (strap option,
LINK_3
COL[2]=1), this output pin is driven low when an interrupt condition is detected within
the Quad Transceiver. An interrupt can occur when link status changes or during jabber
condition. This is an open-drain output. And requires an external pull-up resistor.
Link Lost Status Port 3: When “Disable Management Interface” mode is selected,
(strap option, COL[2]=0), this pin outputs the link lost status for port 3. If link is lost, this
output is high.
LINK_2
LINK_1
90 O, pull-up Link Lost Status Ports 1,2: These pins indicate the link lost status for ports 1 and 2.
89 O, pull-up (During both management interface disable and enable modes)
LINK_1 is also the strap option for RXD levels during idle . S ee Table7 on page11. A
2.7 kpulldown resistor is needed to set RXD_IDLE = High. Default is LINK_1=’1’ and
RXD_IDLE= Low
Table 2. NETWORK INTERFACES: Attachment Unit, Twisted Pair Interface (24 Pins)
Symbol Pins Type
Description
RXI4+
RXI4-
RXI3+
RXI3-
RXI2+
RXI2-
RXI1+
RXI1-
29 I Twisted Pair Receive Input: This differential input pair receives the incoming data from
30 the twisted pair medium via an isolation transformer.
19
20
17
18
7
8
TXU4+
TXU4-
TXU3+
TXU3-
TXU2+
TXU2-
TXU1+
TXU1-
25 O UTP Transmit Outputs: This pair of drivers provide pre-emphasized and filtered differ-
26 ential output for UTP (100 ohm cable). These drivers maintain the same common mode
23 voltage during data transmission and idle mode.
24
13
14
11
12
Reserved 33
I Reserved: This pin must be left unconnected.
ROC
34 I On Chip Reference: An external resistor connects to ground for an on chip reference.
The resistor must be a precision (1%) resistor, the value of which should be determined
by each user to center VOD around 5 Vpp.
Attachment Unit Interface
RX+
RX-
5 I Port 1 Full AUI Receive Input: In AUI mode this differential input pair receives the in-
6 coming data from the AUI medium via an isolation transformer.
TX+ 1 O Port 1 Full AUI Transmit Output: In AUI mode this differential pair sends encoded data
TX- 2
from the AUI transceiver. These outputs are source followers and require 270 Ohm pull
down resistors.
CD+
CD-
34 I Port 1 Full AUI Collision Detect : In AUI mode, this differential input pair receives the
collision detect signals from the AUI medium via an isolation transformer.
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DP83924 pdf, datenblatt
2.0 Interface Descriptions (Continued)
LED_CLK
LED_DATA
50 ms
act.1 act.2 act.3 act.4 stat.1 stat.2 stat.3 stat.4
Note; act.n - Transmit or Receive activity for port n
stat.n - Port n status
Figure 4. Normal LED Mode Timing Diagram
LED_CLK
LED_DATA
FDX Link FDX Link FDX Link FDX Link TX.1 TX.2 TX.3 TX.4 RX.1 RX2 RX.3 RX.4
coded
coded
coded
coded
Por t.1
Port.2
Port.3
Por t.4
Figure 5. Enhanced Mode LED Timing Diagram
TXU+
TXU-
RXI+
RXI-
ROC
1000pF
10.5
1000pF
10.5
200pF
1:2
~ 1 KOhm
49.949.9
1:1 T1
Common Mode
Chokes may be
required.
0.01µF
TD+
TD-
RD+
RD-
RJ45
All values are typical and
are +/- 1%
Figure 6. Twisted Pair Interface Schematic Diagram
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