PDF AFE8201 Data sheet ( Hoja de datos )

Número de pieza	AFE8201
Descripción	IF Analog-to-Digital Converter with Digital Downconverter
Fabricantes	Burr-Brown Corporation
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No Preview Available ! AFE8201 SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 IF Analog-to-Digital Converter with Digital Downconverter FEATURES D 12-BIT, 80MSPS ADC D INTEGRATED DIGITAL DOWNCONVERTER (DDC): Quadrature Mixer/NCO CIC Decimation Filter FIR Filters D MIXER: 32-BIT FREQUENCY AND PHASE D DECIMATION RATIO: 32 to 4096 D USER PROGRAMMABLE FIR FILTERS WITH 16-BIT COEFFICIENTS D 12-BIT AUXILIARY DAC D DATA INTERFACE COMPATIBLE WITH TI C5x/C6x DSP BUFFERED SERIAL PORT (McBSP): Code Composer Module for Easy Software Generation D SPI CONTROL INTERFACE D 3.3V ANALOG, 1.8V DIGITAL SUPPLY D 1.8V to 3.3V I/O SUPPLY D TQFP-48 APPLICATIONS D SOFTWARE RADIOS D IF RECEIVE CHANNEL D DIGITAL RADIO RECEIVERS D NARROWBAND RECEIVERS DESCRIPTION The AFE8201 consists of a general-purpose, 80MSPS, 12-bit analog-to-digital converter (ADC), a digital downconverter (DDC), and user-programmable digital filters. It is designed to sample narrowband (2.5MHz or less) IF signals and digitally mix, filter, and decimate the signals to baseband. The DDC consists of a digital quadrature mixer followed by a CIC decimation filter and FIR filters. The mixer frequency and initial phase are independently programmed by 32-bit control words. After the CIC filter, the internal I and Q signals are passed on to the first FIR filter, which can implement even, odd, halfband, and arbitrary impulse responses with up to 62 taps using 16-bit coefficients. Following the first FIR filter are two parallel FIR filters that can be used to provide two output streams or interleaved to form one extended filter with up to 262 taps. The AFE8201 also contains a 12-bit general-purpose auxiliary digital-to-analog converter (DAC) for applications such as AGC amplifier control. Control register data as well as decimation filter coefficients are written to the AFE8201 through the industry-standard SPI control interface. The baseband output signals are transported through a general- purpose, high-speed serial interface that is compatible with TI C5x/C6x DSP family buffered serial ports (McBSP). IFP IFM 12−Bit Pipeline ADC Quadrature Mixer CIC Filter N FIR Filter 1 2 NCO AUX Auxiliary DAC Voltage Reference Clock Interface Timing Generator FIR Filter 2A 2 FIR Filter 2B 2 SPI Control Interface DOUT0 DOUT1 DFSO DCLK DIN DFSI REFM VCM REFP VGB MCLK MCLKB PWD SYNC RST_N SCK MOSI MISO CS_N Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. www.ti.com Copyright  2003−2005, Texas Instruments Incorporated 1 page AFE8201 www.ti.com CONTROL INTERFACE TIMING SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 SCK CS_N MOSI MISO tL PARAMETER Maximum SCK Frequency CS_N Leading Time, tL CS_N Trailing Time, tT CS_N Idle Time, tL MOSI to SCK Setup Time, tsu3 MOSI to SCK Hold Time, th3 SCK to MISO Delay Time, td4 tsu3 th3 td4 Figure 3. Control Interface Timing CONDITIONS MIN TYP Trailing CS_N to Leading SCK Trailing SCK to Leading CS_N Leading CS_N to Trailing CS_N 5.0 5.0 5.0 5.0 1.0 1.0 tT tI MAX 1 8.0 UNITS MHz ns ns ns ns ns ns 5 5 Page AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 DCLKO DFSO DOUT0 DOUT1 MSB MSB IA IB LSB QA LSB QB DFSI DIN MSB DAC LSB Figure 13. Data Interface Timing for MODE = 1 When the data interface receives new outputs from the decimation filters, an output cycle is started by asserting DFSO for one DCLKO period. On successive leading edges of DCLKO, the filter output data is shifted out MSB first on DOUT0 (and DOUT1 for MODE = 1), as shown in the timing diagrams. The spacing of the DFSO pulses depends on two settings: the overall decimation ratio R of the DDC and the factor DIV. The number of bits which need to be transmitted in one frame, NBITS, is 64 for MODE = 0 and 32 for MODE = 1. In order to have enough DCLKO cycles between DFSO pulses, the following relationship must be true: R 2DIV w NBITS or ǒ ǓDIV v log2 R NBITS (2) (3) For example, assume the overall decimation ratio, R, for the DDC is 80. For MODE = 0, the largest allowable value for DIV is 0. In other words, if MCLK is 80MHz, for R = 80, DCLKO must be 80MHz so that all of the 64 data bits may be clocked out before the next I and Q data words must be clocked out. For MODE = 1, since only 32 bits need to be clocked out during one cycle, DCLKO can be reduced to 40MHz (which means that DIV may be increased to 1, cutting the frequency of DCLKO in half). DFSI and DIN are used to send control DAC data to the AFE8201. DCLKO supplied by the AFE8201 is used as the serial clock. An input cycle is initiated by holding DFSI high through one rising edge of DCLKO. On the successive 16 leading edges of DCLKO the input data word is read in serially, MSB first. The lower 12 bits of the data word are sent to the DAC as the unsigned DAC input. Note that the input data does not need to bear any timing relationship to the output data, except that both data streams are synchronous with DCLKO. QUADRATURE MIXER/NCO The NCO frequency and initial phase are set by the 32-bit unsigned variables FREQ and PHASE. Each of these variables is set via a pair of control registers; see Figure 14. The I and Q outputs of the mixer are given by: I + ADC Q + ADC sin(2pft ) f) and cos(2pft ) f) (4) (5) where ADC is the output of the IF A/D converter, f is the NCO frequency given by: f + f MCLK FREQ 232 (6) and φ is the NCO phase offset (in radians) given by: f + 2p PHASE 232 (7) 11 11 Page

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