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PDF RS5C62 Data sheet ( Hoja de datos )
| Número de pieza | RS5C62 | |
| Descripción | REAL-TIME CLOCK | |
| Fabricantes | RICOH electronics devices division | |
| Logotipo |  |
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REAL-TIME CLOCK
RP/ RF/ RS5C62
APPLICATION MANUAL
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ELECTRONIC DEVICES DIVISION
NO.EA-012-9803
1 page  
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REAL-TIME CLOCK
RP/RF/RS5C62
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OUTLINE
The RP/RF/RS5C62 are CMOS LSIs which serve microcomputers as real-time clocks providing time, calendar,
and alarm functions in direct coupling with the data buses of CPUs such as 8086 and 68000. A built-in timer counter
acts as a watchdog timer or interrupt timer. They are available in three different types of packages: the DIP type,
the SOP type, and the SSOP type.
FEATURES
• Directly connected to CPU, enabling fast access.
• 4bit bidirectional data bus, and 4bit address bus.
• The oscillator is driven by a constant voltage, so the oscillation frequency is stable even when the power supply
voltage fluctuates.
• Built-in timer counter using internal clock.
• Generates cyclic CPU interrupts, and generates alarm-match interrupts.
• Interrupt flag and interrupt inhibit.
• Clock (hour, minute, second), calendar (leap year, year, month, day, day-of-the-week), alarm (hour, minute).
• 12-or 24-hour mode is selectable.
• Recognizes leap years automatically.
• All clock and alarm data expressed in BCDDcoadtaeSs.heet4U.com
• ±30 seconds adjustment function.
• Determines whether clock data is valid or invalid.
• Consumes very low power due to CMOS technology, so it can be backed up by batteries.
• Power supply voltage between 3.0 to 5.0V.
• Time keeping supply voltage between 2.0 to 6.0V.
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• Package : 18pin DIP for RP5C62, 18pin SOP for RF5C62, 20pin SSOP for RS5C62.
BLOCK DIAGRAM
OSCIN
OSCOUT
OSC
DIV
OSC DETECT
WATCH & CALENDAR
COMPARATOR
INTERRURT
CONTROL
INTR
CE
ALARM REGISTER
CS
TMOUT
RD TIMER
WR CONTROL REGISTER
DATA BUS
CONTROL
ADDRESS BUS ADDRESS
CONTROL
DECODER
VDD
VSS
D0D1D2D3
A0 A1 A2 A3
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RP/RF/RS5C62
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2. Functions of Registers
2.1 Control Register 1 (Bank0/1 at “Dh”)
D3
WTEN
0
D2
ALEN
0
D1
TMR
0
D0
BANK
0
(For write operation)
(For read operation) *1
Bank switching bit
BANK
Function
0 Specifies selection of BANK0 in the address table.
1 Specifies selection of BANK1 in the address table.
Timer resetting bit *2
TMR
Function
0 Specifies no change.
1 Specifies resetting of the timer conditional on restart.
Alarm operation setting bit *3
ALEN
Function
0DataShDeeista4bUle.scaonmalarm interrupt.
1 Enables an alarm interrupt.
Time count operation setting bit *4
WTEN
Function
0 Disables a carry to the 1-second time digit.
1 Enables a carry to the 1-second time digit.
*1) The BANK bit is intended for only write operation and always read as “0”.
*2) The timer frequency can be set by the timer clock selection register.
*3) Setting the ALEN bit to “0” during output of an alarm interrupt from the INTR pin (while it is held low) turns off the INTR pin.
Setting the ALEN bit to “1” in matching between clock time and alarm time drives the INTR pin low within a maximum of 61.1µs.
*4) A 1-second carry with the WTEN bit set to “0” increments the second digit by 1 upon setting of the WTEN bit to “1”. This bit will
automatically be set to “1” upon driving low the CE pin.
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| PDF Descargar | [ Datasheet RS5C62.PDF ] | |
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