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PDF P4C198 Data sheet ( Hoja de datos )
| Número de pieza | P4C198 | |
| Descripción | ULTRA HIGH SPEED 16K x 4 | |
| Fabricantes | ETC | |
| Logotipo |  |
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P4C198/P4C198L, P4C198A/P4C198AL
ULTRA HIGH SPEED 16K x 4
STATIC CMOS RAMS
P4C198/198L, P4C198A/198AL
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 ns (Industrial)
– 15/20/25/35/45 ns (Military)
Low Power Operation (Commercial/Military)
– 715 mW Active – 12/15
– 550/660 mW Active – 20/25/35/45/55
– 193/220 mW Standby (TTL Input)
– 83/110 mW Standby (CMOS Input) P4C198/198A
– 9 mW Standby (CMOS Input)
P4C198L/198AL (Military)
5V ± 10% Power Supply
Data Retention, 10 µA Typical Current from 2.0V
P4C198L/198AL (Military)
Output Enable & Chip Enable Control Functions
– Single Chip Enable P4C198
– Dual Chip Enable P4C198A
Common Inputs and Outputs
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP
– 24-Pin 300 mil SOJ (P4C198 only)
– 28-Pin 350 x 550 mil LCC (P4C198 only)
DESCRIPTION
The P4C198/L and P4C198A/L are 65,536-bit ultra high-
speed static RAMs organized as 16K x 4. Each device
features an active low Output Enable control to eliminate
data bus contention. The P4C198/L also have an active
low Chip Enable (the P4C198A/L have two Chip Enables,
both active low) for easy system expansion. The CMOS
memories require no clocks or refreshing and have equal
access and cycle times. Inputs are fully TTL-compatible.
The RAMs operate from a single 5V ± 10% tolerance
power supply. Data integrity is maintained with supply
voltages down to 2.0V. Current drain is typically 10 µA
from a 2.0V supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low 715
mW active, 193 mW standby.
The P4C198/L and P4C198A/L are available in 24-pin 300
mil DIP and SOJ, and 28-pin 350 x 550 mil LCC packages
providing excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
A
(8)
A
I/O 1
I/O 2
I/O 3
I/O 4
ROW
SELECT
INPUT
DATA
CONTROL
65,536-BIT
MEMORY
ARRAY
COLUMN I/O
CE(CE )
1
(P4C198A ONLY) (CE )
2
WE
OE
COLUMN
SELECT
AA
(6)
PIN CONFIGURATIONS
A0
A1
A2
A3
A4
A5
A6
A7
A8
C E (C E 1)
OE
G ND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 A13
22 A12
21 A11
20 A10
19 A9
18 NC (C E 2)
17 I/O4
16 I/O3
15 I/O2
14 I/O1
13 W E
3 27
A1
42
28 26
NC
A2 5
1 25 A13
A3 6
24 A12
A4 7
23 A11
A5 8
22 A10
A6 9
21 A9
A7 10
20 I/O
A8 11
19 I/O3
C E 12 14 15 16 18 I/O2
13 1 7
DIP (P4, D4), SOJ (J4)
TOP VIEW
P4C198 (P4C198A)
LCC (L5)
TOP VIEW
P4C198 ONLY
Means Quality, Service and Speed
1Q97
71
1 page  
READ CYCLE NO. 2 (ADDRESS Controlled)(5,6)
ADDRESS
DATA OUT
t OH
PREVIOUS DATA VALID
t AA
(10)
t RC
READ CYCLE NO. 3 (C E(12) Controlled)(5,7,8)
P4C198/198L, P4C198A/198AL
DATA VALID
1520 05
CE
DATA OUT
VCC SUPPLY
CURRENT
ICC
ISB
tAC (11)
tLZ (9,11)
t
(11)
PU
tRC
(9,11)
tHZ
DATA VALID
tPD(11)
HIGH IMPEDANCE
Notes:
6. CE (CE 1 CE 2 for P4C198A/L) and OE are LOW READ cycle.
7. OE is LOW for the cycle.
8. ADDRESS must be valid prior to, or coincident with CE (CE 1
and CE for P4C198A/L) transition LOW.
2
9. Transition is measured ± 200mV from steady state voltage
prior to change, with loading as specified in Figure 1.
10. Read Cycle Time is measured from the last valid address to
the first transitioning address.
11. Transitions caused by a chip enable control have similar
delays irrespective of whether CE or CE causes them
12
(P4C198A/L).
12. CE 1, CE 2 for P4C198A/L.
75
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet P4C198.PDF ] | |
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