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P4C188 Schematic ( PDF Datasheet ) - ETC

Teilenummer P4C188
Beschreibung ULTRA HIGH SPEED 16K x 4 STATIC
Hersteller ETC
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Gesamt 8 Seiten
P4C188 Datasheet, Funktion
P4C188/P4C188L
ULTRA HIGH SPEED 16K x 4
STATIC CMOS RAMS
P4C188/188L
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 (Industrial)
– 15/20/25/35/45 ns (Military)
Low Power (Commercial/Military)
– 715 mW Active – 12/15
– 550/660 mW Active – 20/25/35/45
– 193/220 mW Standby (TTL Input)
– 83/110 mW Standby (CMOS Input) P4C188
– 15 mW Standby (CMOS Input)
(P4C188L Military)
Single 5V±10% Power Supply
Data Retention with 2.0V Supply
(P4C188L Military)
Three-State Outputs
TTL/CMOS Compatible Outputs
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 22-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 22-Pin 290 x 490 mil LCC
DESCRIPTION
The P4C188 and P4C188L are 65,536-bit ultra high speed
static RAMs organized as 16K x 4. The CMOS memories
require no clocks or refreshing and have equal access and
cycle times. Inputs and outputs are fully TTL-compatible.
The RAMs operate from a single 5V±10% tolerance power
supply. With battery backup, data integrity is maintained for
supply voltages down to 2.0V. Current drain is typically 10
µA from a 2.0V supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption to a low 715mW
active, 193mW standby and only 5mW in the P4C188L
version.
The P4C188 and P4C188L are available in 22-pin 300 mil
DIP, 24-pin 300 mil SOJ and 22-pin LCC packages provid-
ing excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
A
(8)
A
I/O 1
I/O 2
I/O 3
I/O 4
ROW
SELECT
INPUT
DATA
CONTROL
65,536-BIT
MEMORY
ARRAY
COLUMN I/O
COLUMN
SELECT
CE
AA
(6)
WE
PIN CONFIGURATIONS
A0
A1
A2
A3
A4
A5
A6
A7
A8
CE
GND
1
2
3
4
5
6
7
8
9
10
11
22 V CC
21 A 13
20 A 12
19 A 11
18 A 10
17 A 9
16 I/O 4
15 I/O 3
14 I/O 2
13 I/O 1
12 WE
2 21
A2 3
22 20
1
A3 4
19
A4 5
18
A5 6
17
A6 7
16
A7 8
15
A 8 9 11 12 14
10 13
A 12
A 11
A 10
A9
I/O 4
I/O 3
I/O 2
DIP (P3, D3)
TOP VIEW
LCC (L3)
TOP VIEW
For SOJ pin configuration, please see Selection Guide Page.
Means Quality, Service and Speed
1Q97
63






P4C188 Datasheet, Funktion
P4C188/188L
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(9)
ADDRESS
CE
WE
DATA IN
(11)
t WC
t AS t CW
t AW
t WP
t AH
t WR
t DW
DATA VALID
t DH
DATA OUT
HIGH IMPEDANCE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
TRUTH TABLE
Mode
CE
Standby H
Read
L
Write
L
WE
X
H
L
Output
High Z
D
OUT
D
IN
Power
Standby
Active
Active
DOUT
255
+5V
480
30pF**(5pF* for tHHZZ,,tLt ZL,Z ,
ttWWZZanadndtOWtO)W )
D OUT
RTH = 166.5
VTH = 1.73 V
30pF* (5pF* for t HZ , t LZ ,
t WZ and tOW )
Figure 1. Output Load
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C188/L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the VCC and ground
planes directly up to the contactor fingers. A 0.01 µF high frequency
Figure 2. Thevenin Equivalent
capacitor is also required between VCC and ground. To avoid signal
reflections, proper termination must be used; for example, a 50test
environment should be terminated into a 50load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116resistor must be used in
series with DOUT to match 166(Thevenin Resistance).
68

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