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P4C1024-17P3I Schematic ( PDF Datasheet ) - ETC

Teilenummer P4C1024-17P3I
Beschreibung HIGH SPEED 128K X 8 CMOS STATIC RAM
Hersteller ETC
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Gesamt 8 Seiten
P4C1024-17P3I Datasheet, Funktion
P4C1024
HIGH SPEED 128K x 8
CMOS STATIC RAM
P4C1024
FEATURES
High Speed (Equal Access and Cycle Times)
— 15/17/20/25/35 ns (Commercial)
— 20/25/35/45 ns (Industrial)
Single 5 Volts ±10% Power Supply
Easy
Memory
Expansion
Using
CE
1,
CE2
and
OE Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
—32-Pin 300 mil DIP and SOJ
—32-Pin 400 mil SOJ
DESCRIPTION
The P4C1024 is a 1,048,576-bit high-speed CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 15 nanoseconds permit greatly en-
hanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The P4C1024
is a member of a family of PACE RAM™ products offer-
ing fast access times.
The P4C1024 device provides asynchronous opera-
tions with matching access and cycle times. Memory
locations are specified on address pins A0 to A16. Read-
ing is accomplished by device selection (CE low and
1
CE high) and output enabling (OE) while write enable
2
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory
location is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE
1
or
OE
is
HIGH
or
WE
or
CE2
is
LOW.
Package options for the P4C1024 include 32-pin 300
mil DIP and SOJ packages as well as 400 mil SOJ.
FUNCTIONAL BLOCK DIAGRAM
A
(9)
A
I/O1
I/O2
INPUT
DATA
CONTROL
262,144-
BIT
MEMORY
ARRAY
COLUMN
I/O
WE
CE1
CE2
OE
CONTROL
CIRCUIT
COLUMN
SELECT
••• •••
A (8)
A
1024.1
PIN CONFIGURATION
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
1024.2
DIP (P300), SOJ (J300, J400)
TOP VIEW
Means Quality, Service and Speed
1Q97
141






P4C1024-17P3I Datasheet, Funktion
P4C1024
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6)
ADDRESS
CE1
tWC (9)
tAS tCW
tAW
tAH
CE2
WE
DATA IN
t WP
tDW
DATA VALID
tDH
(12)
DATA OUT
HIGH IMPEDANCE
AC TEST CONDITIONS
TRUTH TABLE
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
Output Timing Reference Level
1.5V
1.5V
Output Load
See Figures 1 and 2
Mode
Standby
Standby
CE
1
CE2
OE
WE
I/O
Power
H X X X High Z Standby
X L X X High Z Standby
DOUT Disabled L H H H High Z Active
Read
Write
L H L H DOUT Active
L H X L High Z Active
D OUT
255
+5V
480
30pF* (5pF* for t HZ , t LZ , t OHZ ,
t OLZ , t WZ and t OW )
D OUT
RTH = 166.5
VTH = 1.73 V
30pF* (5pF* for t HZ , t LZ , t OHZ,
t OLZ, t WZ and t OW )
Figure 1. Output Load
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1024, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground.
Figure 2. Thevenin Equivalent
To avoid signal reflections, proper termination must be used; for
example, a 50test environment should be terminated into a 50
load with 1.73V (Thevenin Voltage) at the comparator input, and a
116resistor must be used in series with DOUT to match 166
(Thevenin Resistance).
146

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