|
|
Teilenummer | P2V28S30ATP-7 |
|
Beschreibung | 128Mb SDRAM Specification | |
Hersteller | Vanguard International Semiconductor | |
Logo | ||
Gesamt 51 Seiten 128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
128Mb SDRAM Specification
P2V28S20DTP-7,-75,-8
P2V28S30DTP-7,-75,-8
P2V28S40DTP-7,-75,-8
JULY.2000
MIRA TECHNOLOGY INC.
8F.,68,SEC.3,NANKING E.RD.,TAIPEI,TAIWAN,R.O.C.
TEL:886-2-25170055.25170066
FAX:886-2-25174575
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
BASIC FUNCTIONS
The P2V28S20 , 30 and 40ATP provides basic functions,
bank (row) activate, burst read / write, bank (row) precharge,
and auto / self refresh.
Each command is defined by control signals of /RAS, /CAS and
/WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and
A10 are used as chip select, refresh opt ion, and precharge
option, respectively .
To know the detailed definition of commands, please see the com-
mand truth table.
CLK
/CS
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
define basic command
Command
Refresh Option @ refresh command
Precharge Option @ precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output
data appears after /CAS latency. When A10 =H at this command, the bank is deac-
tivated after the burst read (auto-precharge, READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, all banks
are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
JULY.2000
Page-5
Rev.2.2
6 Page 128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
Command Action
WRITE
H X X XX
RECOVERING
L
H H HX
DESEL NOP
NOP NOP
L H H L BA
TBST ILLEGAL*2
L H L X BA, CA, A10 READ / ILLEGAL*2
WRITE
L L H H BA, RA
ACT ILLEGAL*2
L L H L BA, A10
PRE / ILLEGAL*2
PREA
L L L HX
REFA ILLEGAL
L L L L Op-Code,
Mode-Add
MRS ILLEGAL
REFRESHING H X X X X
DESEL NOP (Idle after tRC)
L H H HX
NOP NOP (Idle after tRC)
L H H L BA
TBST ILLEGAL
L H L X BA, CA, A10 READ / ILLEGAL
WRITE
L L H H BA, RA
ACT ILLEGAL
L L H L BA, A10
PRE /
PREA
ILLEGAL
L L L HX
REFA ILLEGAL
L L L L Op-Code,
Mode-Add
MRS ILLEGAL
JULY.2000
Page-11
Rev.2.2
12 Page | ||
Seiten | Gesamt 51 Seiten | |
PDF Download | [ P2V28S30ATP-7 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
P2V28S30ATP-7 | 128Mb SDRAM Specification | Vanguard International Semiconductor |
P2V28S30ATP-75 | 128Mb SDRAM Specification | Vanguard International Semiconductor |
P2V28S30ATP-8 | 128Mb SDRAM Specification | Vanguard International Semiconductor |
Teilenummer | Beschreibung | Hersteller |
CD40175BC | Hex D-Type Flip-Flop / Quad D-Type Flip-Flop. |
Fairchild Semiconductor |
KTD1146 | EPITAXIAL PLANAR NPN TRANSISTOR. |
KEC |
www.Datenblatt-PDF.com | 2020 | Kontakt | Suche |