Datenblatt-pdf.com


8XC552 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer 8XC552
Beschreibung 80C51 FAMILY DERIVATIVES
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
8XC552 Datasheet, Funktion
INTEGRATED CIRCUITS
80C51 FAMILY DERIVATIVES
8XC552/562 overview
1996 Aug 06
Philips
Semiconductors






8XC552 Datasheet, Funktion
Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
TM2CON (EAH)
7
T2IS1
(MSB)
6
T2IS0
5
T2ER
4
T2BO
3
T2P1
2
T2P0
10
T2MS1 T2MS0
(LSB)
BIT
TM2CON.7
TM2CON.6
TM2CON.5
SYMBOL
TSIS1
T2IS0
T2ER
TM2CON.4
TM2CON.3
TM2CON.2
T2BO
T2P1
T2P0
FUNCTION
Timer T2 16-bit overflow interrupt select
Timer T2 byte overflow interrupt select
Timer T2 external reset enable. When this bit is set,
Timer T2 may be reset by a rising edge on RT2 (P1.5).
Timer T2 byte overflow interrupt flag
Timer T2 prescaler select
T2P1
0
0
1
1
T2P0
0
1
0
1
Timer T2 Clock
Clock source
Clock source/2
Clock source/4
Clock source/8
TM2CON.1
TM2CON.0
T2MS1
T2MS0
Timer T2 mode select
T2MS1 T2MS0
00
01
10
11
Mode Selected
Timer T2 halted (off)
T2 clock source = fOSC/12
Test mode; do not use
T2 clock source = pin T2
Figure 3. T2 Control Register (TM2CON)
SU00756
Timer T2 Extension: When a 12MHz oscillator is used, a 16-bit
overflow on Timer T2 occurs every 65.5, 131, 262, or 524 ms,
depending on the prescaler division ratio; i.e., the maximum cycle
time is approximately 0.5 seconds. In applications where cycle times
are greater than 0.5 seconds, it is necessary to extend Timer T2.
This is achieved by selecting fosc/12 as the clock source (set
T2MS0, reset T2MS1), setting the prescaler division ration to 1/8
(set T2P0, set T2P1), disabling the byte overflow interrupt (reset
T2IS0) and enabling the 16-bit overflow interrupt (set T2IS1). The
following software routine is written for a three-byte extension which
gives a maximum cycle time of approximately 2400 hours.
OVINT: PUSH
PUSH
INC
MOV
JNZ
ACC ;save accumulator
PSW ;save status
TIMEX1 ;increment first byte (low order)
;of extended timer
A,TIMEX1
INTEX ;jump to INTEX if ;there is no overflow
INC
MOV
JNZ
INC
TIMEX2 ;increment second byte
A,TIMEX2
INTEX ;jump to INTEX if there is no overflow
TIMEX3 ;increment third byte (high order)
INTEX: CLR
POP
POP
RETI
T2OV
PSW
ACC
;reset interrupt flag
;restore status
;restore accumulator
;return from interrupt
Timer T2, Capture and Compare Logic: Timer T2 is connected to
four 16-bit capture registers and three 16-bit compare registers. A
capture register may be used to capture the contents of Timer T2
when a transition occurs on its corresponding input pin. A compare
register may be used to set, reset, or toggle port 4 output pins at
certain pre-programmable time intervals.
The combination of Timer T2 and the capture and compare logic is
very powerful in applications involving rotating machinery,
automotive injection systems, etc. Timer T2 and the capture and
compare logic are shown in Figure 4.
Capture Logic: The four 16-bit capture registers that Timer T2 is
connected to are: CT0, CT1, CT2, and CT3. These registers are
loaded with the contents of Timer T2, and an interrupt is requested
upon receipt of the input signals CT0I, CT1I, CT2I, or CT3I. These
input signals are shared with port 1. The four interrupt flags are in
the Timer T2 interrupt register (TM2IR special function register). If
the capture facility is not required, these inputs can be regarded as
additional external interrupt inputs.
Using the capture control register CTCON (see Figure 5), these
inputs may capture on a rising edge, a falling edge, or on either a
rising or falling edge. The inputs are sampled during S1P1 of each
cycle. When a selected edge is detected, the contents of Timer T2
are captured at the end of the cycle.
1996 Aug 06
6

6 Page









8XC552 pdf, datenblatt
Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
I2C bus
VDD
RP RP
SDA
SCL
P1.7/SDA P1.6/SCL
8XC552
Other Device with
I2C Interface
Other Device with
I2C Interface
Figure 10. Typical I2C Bus Configuration
SDA
MSB
Slave Address
SCL
S
Start
Condition
1
2
R/W
Direction
Bit
Acknowledgment
Signal from Receiver
Acknowledgment
Signal from Receiver
Clock Line Held Low While
Interrupts Are Serviced
7 89
ACK
1 2 3–8 9
ACK
Repeated if more bytes
are transferred
Figure 11. Data Transfer on the I2C Bus
Stop
Condition
Repeated
Start
Condition
P/S
1996 Aug 06
12

12 Page





SeitenGesamt 30 Seiten
PDF Download[ 8XC552 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
8XC55280C51 FAMILY DERIVATIVESNXP Semiconductors
NXP Semiconductors

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche