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8XC51FB Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer 8XC51FB
Beschreibung Low power single card reader
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
8XC51FB Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
TDA8029
Low power single card reader
Product specification
2003 Oct 30






8XC51FB Datasheet, Funktion
Philips Semiconductors
Low power single card reader
Product specification
TDA8029
7 PINNING
SYMBOL
P17
P16
VDD
GND
SDWN_N
CDEL
I/O
PRES
GNDC
CLK
VCC
RST
VUP
SAP
SBP
DCIN
SBM
PGND
SAM
TEST
EA_N
ALE
PSEN_N
P27
P26
XTAL1
XTAL2
RESET
P32/INT0_N
P33/INT1_N
P31/TX
P30/RX
PIN DESCRIPTION
1 general purpose I/O
2 general purpose I/O; card clock generation up to 20 MHz with three times synchronous
frequency doubling (fXTAL, 1/2fXTAL, 1/4fXTAL and 1/8fXTAL)
3 supply voltage
4 ground connection
5 shut-down signal input; active LOW
6 connection for an external capacitor determining the Power-on reset pulse width
(typically 1 ms per 2 nF)
7 data input/output to/from the card (C7); 14 kintegrated pull-up resistor to VCC
8 card presence detection contact (active HIGH); do not connect to any external pull-up
or pull-down resistor; use with a normally open presence switch
9 card ground (C5); connect to GND in the application
10 clock to the card (C3)
11 card supply voltage (C1)
12 card reset (C2)
13 output of the DC/DC converter (low ESR 220 nF to PGND)
14 DC/DC converter capacitor connection (low ESR 220 nF between SAP and SAM)
15 DC/DC converter capacitor connection (low ESR 220 nF between SBP and SBM)
16 power input for the DC/DC converter
17 DC/DC converter capacitor connection (low ESR 220 nF between SBP and SBM)
18 ground for the DC/DC converter
19 DC/DC converter capacitor connection (low ESR 220 nF between SAP and SAM)
20 used for test purpose; connect to GND in the application
21 control signal for microcontroller; connect to VDD in the application
22 control signal for the microcontroller; leave open in the application
23 control signal for the microcontroller; leave open in the application
24 general purpose I/O
25 general purpose I/O
26 external crystal connection or input for an external clock signal
27 external crystal connection; leave open if an external clock is applied to XTAL1
28 reset input from the host (active HIGH); integrated pull-down resistor to GND
29 interrupt signal from the smart card interface; leave open in the application
30 external interrupt input or general purpose I/O; may be left open if not used
31 transmission line for serial communication with the host
32 reception line for serial communication with the host
2003 Oct 30
6

6 Page









8XC51FB pdf, datenblatt
Philips Semiconductors
Low power single card reader
Product specification
TDA8029
this mode. The Idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up
at the interrupt service routine and continued), or by a
hardware reset which starts the processor in the same
manner as a Power-on reset.
Power-down mode: To save even more power, a
Power-down mode can be invoked by software. In this
mode, the oscillator is stopped and the instruction that
invoked Power-down is the last instruction executed.
Either a hardware reset, external interrupt or reception
on RX can be used to exit from Power-down mode. Reset
redefines all the SFRs but does not change the on-chip
RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values.
With INT0_N, INT1_N or RX, the bits in register IE must be
enabled. Within the INT0_N interrupt service routine, the
controller has to read out the Hardware Status Register
(HSR @ 0Fh) and/or the UART Status register
(USR @ 0Eh) by means of MOVX-instructions in order to
know the exact interrupt reason and to reset the interrupt
source.
For enabling a wake up by INT1_N, the bit ENINT1 within
UCR2 must be set.
For enabling a wake up by RX, the bits ENINT1 and ENRX
within UCR2 must be set.
An integrated delay counter maintains internally INT0_N
and INT1_N LOW long enough to allow the oscillator to
restart properly, so a falling edge on pins RX, INT0_N and
INT1_N is enough for awaking the whole circuit.
Once the interrupt is serviced, the next instruction to be
executed after RETI will be the one following the
instruction that put the device into power-down.
Table 3 External pin status during Idle and Power-down mode
MODE
Idle
Power-down
PROGRAM MEMORY
internal
external
internal
external
ALE
1
1
0
0
PSEN_N PORT 0 PORT 1 PORT 2 PORT 3
1 data data data data
1 float data address data
0 data data data data
0 float data data data
2003 Oct 30
12

12 Page





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