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8XC251TQ Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer 8XC251TQ
Beschreibung HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
8XC251TQ Datasheet, Funktion
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ
HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Commercial/Express
s Real-time and Programmed Wait State
Bus Operation
s Binary-code Compatible with MCS® 51
s Pin Compatible with 44-pin PLCC and
40-pin PDIP MCS 51 Sockets
s Register-based MCS® 251 Architecture
— 40-byte Register File
— Registers Accessible as Bytes,
Words, or Double Words
s Enriched MCS 51 Instruction Set
— 16-bit and 32-bit Arithmetic and
Logic Instructions
— Compare and Conditional Jump
Instructions
— Expanded Set of Move Instructions
s Linear Addressing
s 256-Kbyte Expanded External
Code/Data Memory Space
s ROM Options:
16 Kbytes (TB/TQ), 8 Kbytes (TA/TP), or
without ROM
s 16-bit Internal Code Fetch
s 64-Kbyte Extended Stack Space
s On-chip Data RAM Options:
1-Kbyte (TA/TB) or 512-Byte (TP/TQ)
s 8-bit, 2-clock External Code Fetch in
Page Mode
s Fast MCS 251 Instruction Pipeline
s User-selectable Configurations:
— External Wait States (0-3 wait
states)
— Address Range & Memory Mapping
— Page Mode
— Extended Data Float Timings or
8xC251Sx Compatible AC Timings
s 32 Programmable I/O Lines
s Eight Maskable Interrupt Sources with
Four Programmable Priority Levels
s Three Flexible 16-bit Timer/counters
s Hardware Watchdog Timer
s Programmable Counter Array
— High-speed Output
— Compare/Capture Operation
— Pulse Width Modulator
— Watchdog Timer
s Two Programmable Serial I/O Ports
— Framing Error Detection
— Automatic Address Recognition
s High-performance CHMOS Technology
s Static Standby to 24-MHz Operation
s Complete System Development
Support
— Compatible with Existing Tools
— MCS 251 Tools Available:
Compiler, Assembler, Debugger,
ICE
s Package Options (PDIP and PLCC)
© INTEL CORPORATION, 1997
November, 1997
Order Number: 273129-001






8XC251TQ Datasheet, Funktion
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
2.0 NOMENCLATURE
X XX 8 X X XXXXX XX
A2815-01
Figure 2. The 8xC251TA/TB/TP/TQ Family Nomenclature
Table 1. Description of Product Nomenclature
Parameter
Temperature and Burn-in
Options
Packaging Options
Program Memory Options
Process Information
Product Family
Device Memory Options
Device Speed
Options
no mark
T
N
P
C
0
3
C
251
TA
TB
TP
TQ
24
Description
Commercial operating temperature range (0°C to 70°C) with
Intel standard burn-in.
Express operating temperature range (-40°C to 85°C)
without Intel standard burn-in.
44-pin Plastic Leaded Chip Carrier (PLCC)
40-pin Plastic Dual In-line Package (PDIP)
40-pin Ceramic Dual In-line Package (Ceramic DIP)
Without ROM
ROM
CHMOS
8-bit control architecture
1-Kbyte RAM/8-Kbyte ROM
1-Kbyte RAM/16-Kbyte ROM or without ROM
512-byte RAM/8-Kbyte ROM
512-byte RAM/16-Kbyte ROM or without ROM
External clock frequency
2 ADVANCE INFORMATION

6 Page









8XC251TQ pdf, datenblatt
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
4.0 SIGNALS
Signal
Name
A17
A16
A15:81
AD7:01
ALE
CEX4:0
EA#
ECI
INT1:0#
P0.7:0
P1.0
P1.1
P1.2
P1.7:3
P2.7:0
P3.0
P3.1
P3.3:2
P3.5:4
P3.6
P3.7
PSEN#
Table 6. Signal Descriptions (Sheet 1 of 3)
Type
O
O
O
I/O
O
I/O
I
I
I
I/O
I/O
I/O
I/O
O
Description
18th Address Bit (A17). Output to memory as 18th external address bit
(A17) in extended bus applications, depending on the values of bits RD0
and RD1 in configuration byte UCONFIG0. See also RD# and PSEN#.
Address Line 16. See RD#.
Address Lines. Upper address lines for the external bus.
Address/Data Lines. Multiplexed lower address lines and data lines for
external memory.
Address Latch Enable. ALE signals the start of an external bus cycle
and indicates that valid address information is available on lines A15:8
and AD7:0. An external latch can use ALE to demultiplex the address
from the address/data bus.
Programmable Counter Array (PCA) Input/Output Pins. These are
input signals for the PCA capture mode and output signals for the PCA
compare mode and PCA PWM mode.
External Access. Directs program memory accesses to on-chip or off-
chip code memory. For EA# = 0, all program memory accesses are off-
chip. For EA# = 1, an access is to on-chip ROM if the address is within
the range of the on-chip ROM; otherwise the access is off-chip. The value
of EA# is latched at reset. For devices without on-chip ROM, EA# must
be strapped to ground.
PCA External Clock Input. External clock input to the 16-bit PCA timer.
External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON
register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a
falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are set by
a low level on INT1:0#.
Port 0. This is an 8-bit, open-drain, bidirectional I/O port.
Port 1. This is an 8-bit, bidirectional I/O port with internal pullups.
Port 2. This is an 8-bit, bidirectional I/O port with internal pullups.
Port 3. This is an 8-bit, bidirectional I/O port with internal pullups.
Program Store Enable. Read signal output. This output is asserted for a
memory address range that depends on bits RD0 and RD1 in configu-
ration byte UCONFIG0 (see RD#).
Alternate
Function
P1.7/CEX4/
WCLK
RD#
P2.7:0
P0.7:0
P1.6:4
P1.7/A17/
WAIT#
P1.3/TXD1
P1.2/RXD1
P3.3:2
AD7:0
T2
T2EX
ECI/RXD1
CEX3:1
CEX4/A17/
WAIT#/
WCLK
CEX0/TXD1
A15:8
RXD
TXD
INT1:0#
T1:0
WR#
RD#/A16
8 ADVANCE INFORMATION

12 Page





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