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89S8252 Schematic ( Datenblatt PDF ) - ATMEL Corporation

Teilenummer 89S8252
Beschreibung 8-Bit Microcontroller with 8K Bytes Flash
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 

Gesamt 30 Seiten
		
89S8252 Datasheet, Funktion
Features
Compatible with MCS-51™ Products
8K Bytes of In-System Reprogrammable Downloadable Flash Memory
– SPI Serial Interface for Program Downloading
– Endurance: 1,000 Write/Erase Cycles
2K Bytes EEPROM
– Endurance: 100,000 Write/Erase Cycles
4.0V to 6V Operating Range
Fully Static Operation: 0 Hz to 24 MHz
Three-Level Program Memory Lock
256 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Nine Interrupt Sources
Programmable UART Serial Channel
SPI Serial Interface
Low Power Idle and Power Down Modes
Interrupt Recovery From Power Down
Programmable Watchdog Timer
Dual Data Pointer
Power Off Flag
Description
The AT89S8252 is a low-power, high-performance CMOS 8-bit microcomputer with
8K bytes of Downloadable Flash programmable and erasable read only memory and
2K bytes of EEPROM. The device is manufactured using Atmel’s high density nonvol-
atile memory technology and is compatible with the industry standard 80C51 instruc-
tion set and pinout. The on-chip Downloadable Flash allows the program memory to
be reprogrammed in-system through an SPI serial interface or by a conventional non-
volatile memory programmer. By combining a versatile 8-bit CPU with Downloadable
Flash on a monolithic chip, the Atmel AT89S8252 is a powerful microcomputer which
provides a highly flexible and cost effective solution to many embedded control appli-
cations.
The AT89S8252 provides the following standard features: 8K bytes of Downloadable
Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watch-
dog timer, two Data Pointers, three 16-bit timer/counters, a six-vector two-level inter-
rupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In
addition, the AT89S8252 is designed with static logic for operation down to zero fre-
quency and supports two software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt sys-
tem to continue functioning. The Power Down Mode saves the RAM contents but
freezes the oscillator, disabling all other chip functions until the next interrupt or hard-
ware reset.
The Downloadable Flash can be changed a single byte at a time and is accessible
through the SPI serial interface. Holding RESET active forces the SPI bus into a serial
programming interface and allows the program memory to be written to or read from
unless Lock Bit 2 has been activated.
8-Bit
Microcontroller
with 8K Bytes
Flash
AT89S8252
0401D-A–12/97
4-105






89S8252 Datasheet, Funktion
User software should not write 1s to these unlisted loca-
tions, since they may be used in future products to invoke
new features. In that case, the reset or inactive values of the
new bits will always be 0.
Timer 2 Registers Control and status bits are contained in
registers T2CON (shown in Table 2) and T2MOD (shown in
Table 9) for Timer 2. The register pair (RCAP2H, RCAP2L)
are the Capture/Reload registers for Timer 2 in 16 bit cap-
ture mode or 16-bit auto-reload mode.
Watchdog and Memory Control Register The WMCON
register contains control bits for the Watchdog Timer
(shown in Table 3). The EEMEN and EEMWE bits are used
to select the 2K bytes on-chip EEPROM, and to enable
byte-write. The DPS bit selects one of two DPTR registers
available.
SPI Registers Control and status bits for the Serial Periph-
eral Interface are contained in registers SPCR (shown in
Table 4) and SPSR (shown in Table 5). The SPI data bits
are contained in the SPDR register. Writing the SPI data
register during serial data transfer sets the Write Collision
bit, WCOL, in the SPSR register. The SPDR is double buff-
ered for writing and the values in SPDR are not changed by
Reset.
Interrupt Registers The global interrupt enable bit and the
individual interrupt enable bits are in the IE register. In addi-
tion, the individual interrupt enable bit for the SPI is in the
SPCR register. Two priorities can be set for each of the six
interrupt sources in the IP register.
Table 2. T2CON—Timer/Counter 2 Control Register
T2CON Address = 0C8H
Bit Addressable
TF2
EXF2
RCLK
TCLK
Bit 7 6 5 4
EXEN2
3
Reset Value = 0000 0000B
TR2
C/T2
CP/RL2
210
Symbol
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Function
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either
RCLK = 1 or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock.
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if
Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
Start/Stop control for Timer 2. TR2 = 1 starts the timer.
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
4-110 AT89S8252

6 Page







89S8252 pdf, datenblatt
Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)
Figure 4. Timer 2 in Baud Rate Generator Mode
TIMER 1 OVERFLOW
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12
OSC
÷2
C/T2 = 0
T2 PIN
T2EX PIN
C/T2 = 1
TRANSITION
DETECTOR
TH2
CONTROL
TR2
TL2
RCAP2H RCAP2L
CONTROL
EXEN2
EXF2
÷2
"0" "1"
SMOD1
"1" "0"
"1" "0"
TIMER 2
INTERRUPT
RCLK
÷16
Rx
CLOCK
TCLK
÷ 16
Tx
CLOCK
4-116 AT89S8252

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