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89C5X Schematic ( PDF Datasheet ) - ETC

Teilenummer 89C5X
Beschreibung FlashFlex51 MCU
Hersteller ETC
Logo ETC Logo 




Gesamt 30 Seiten
89C5X Datasheet, Funktion
FlashFlex51 MCU
SST89C54 / SST89C58
FEATURES:
SST89C5xFlashFlex51 MCU
Data Sheet
• 8-bit 8051-Compatible Microcontroller (MCU)
with Embedded SuperFlash Memory
– Fully Software Compatible
– Development Toolset Compatible
– Pin-For-Pin Package Compatible
• SST89C54/58 Operation
– 0 to 33MHz at 5V
• 256 Bytes Internal RAM
• Dual Block SuperFlash EEPROM
– SST89C58:
32 KByte primary block (128-Byte sector size) +
4 KByte secondary block (64-Byte sector size)
– SST89C54:
16 KByte primary block (128-Byte sector size) +
4 KByte secondary block (64-Byte sector size)
– Individual Block Security Lock with SoftLock
– Concurrent operation during
In-Application Programming (IAP)
– Memory Re-mapping for Interrupt Support
during IAP
• Support External Address Range up to 64
KByte of Program and Data Memory
• Three High Current Drive Ports (16 mA each)
• Three 16-bit Timers/Counters
• Full-Duplex Serial Port (UART)
• Six Interrupt Sources at 2 Priority Levels
• Programmable Watchdog Timer (WDT)
• Four 8-bit I/O Ports (32 I/O Pins)
• TTL- and CMOS-Compatible Logic Levels
• Low Power Modes
– Power-down Mode with External Interrupt Wake-up
– Standby (Stop Clock)
• Low Voltage at 2.7V (0 to 12MHz)
• PDIP-40, PLCC-44 and TQFP-44 Packages
• Temperature Ranges:
– Commercial (0°C to +70°C)
– Industrial (-40°C to +85°C)
PRODUCT DESCRIPTION
The SST89C54 and SST89C58 are members of the
FlashFlex51 family of 8-bit microcontroller products
designed and manufactured with the state-of-the-art
SuperFlash CMOS semiconductor process technology.
The device uses the same 8051 instruction set and is pin-
for-pin compatible with standard 8051 microcontroller
devices.
The device comes with 20/36 KByte of on-chip flash
EEPROM program memory using SST’s patented and pro-
prietary CMOS SuperFlash EEPROM technology with
SST’s field-enhancing, tunneling injector, split-gate memory
cells. The SuperFlash memory is partitioned into 2 indepen-
dent program memory blocks. The primary SuperFlash
Block 0 occupies 16/32 KByte of internal program memory
space and the secondary SuperFlash Block 1 occupies 4
KByte of internal program memory space. The 4 KByte
secondary SuperFlash block can be mapped to the highest
or lowest location of the 64 KByte address space; it can also
be hidden from the program counter and used as an inde-
pendent EEPROM-like data memory. The flash memory
blocks can be programmed via a standard 87C5x OTP
EPROM programmer fitted with a special adapter and firm-
ware for SST’s devices. During the power-on reset, the
device can be configured as a slave to an external host for
source code storage or as a master to an external host for
an in-application programming (IAP) operation. The device
is designed to be programmed in-system and in-application
on the printed circuit board for maximum flexibility. The
device is pre-programmed with an example of the bootstrap
loader in the memory, demonstrating the initial user pro-
gram code loading or subsequent user code updating via
the IAP operation. An example of bootstrap loader is avail-
able for the user’s reference and convenience only. SST
does not guarantee the functionality nor the usefulness of
the sample bootstrap loader. Chip-Erase operations will
erase the pre-programmed sample code.
In addition to 20/36 KByte of SuperFlash EEPROM pro-
gram memory on-chip, the device can address up to 64
KByte of external program memory. In addition to 256 x8
bits of on-chip RAM, up to 64 KByte of external RAM can
be addressed.
SST’s highly reliable, patented SuperFlash technology
and memory cell architecture have a number of impor-
tant advantages for designing and manufacturing flash
EEPROMs. These advantages translate into signifi-
cant cost and reliability benefits for our customers.
©2002 Silicon Storage Technology, Inc.
S71131-03-000 9/02
344
1
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.






89C5X Datasheet, Funktion
Data Sheet
1.0 FUNCTIONAL BLOCKS
FUNCTIONAL BLOCK DIAGRAM
FlashFlex51 MCU
SST89C54 / SST89C58
Oscillator
8051
CPU Core
Watchdog Timer
Interrupt
Control
6 Interrupts
FCU
SuperFlash
EEPROM
Primary
Block
16K/32K x81
Secondary
Block
4K x8
Security
Lock
Timer 0 (16-bit)
Timer 1 (16-bit)
Timer 2 (16-bit)
RAM
256 x8
I/O Port 0
I/O Port 1
I/O Port 2
I/O Port 3
8
I/O
8
I/O
8
I/O
8
I/O
8-bit
UART
344 ILL B1.2
1. 16K x 8 for SST89C54
32K x 8 for SST89C58
FCU = Flash Control Unit
8051 CPU Core = ALU, ACC, B-Reg., Instruction Reg., PC, Timing and Control, etc.
©2002 Silicon Storage Technology, Inc.
6
S71131-03-000 9/02 344

6 Page









89C5X pdf, datenblatt
Data Sheet
3.2 Memory Re-mapping
The SST89C54/58 memory re-mapping feature allows
users to re-map the secondary flash memory block physi-
cal address to overlay the lower order logical address so
that interrupts can be serviced when the primary flash
memory block (Block 0) is busy under Program/Erase
operation.
Since Block 0 occupies the low order program address
space of the 8051 architecture where the interrupt vectors
reside, those interrupt vectors will normally not be available
when Block 0 is being programmed.
SST89C54/58 provides four options of memory re-map-
ping (Refer to Table 3-1). When the lowest 4 KByte are re-
mapped, any program access within logical address range
0000H-0FFFH will have the 4 most significant address bits
forced to “1”, redirecting the access to F000H-FFFFH. Note
that the physical contents of the overlaid portion of Block 0
(i.e. physical locations 0000H-0FFFH in the current exam-
ple) will not be addressable by the program counter, but
only accessible through IAP registers. Block 1 is still acces-
sible through F000H-FFFFH. Block 1 is addressable by the
program counter in both logical address ranges 0000H-
0FFFH and F000H-FFFFH.
FlashFlex51 MCU
SST89C54 / SST89C58
3.2.1 Activation and Deactivation of
Memory Re-mapping
The actual amount of memory that is re-mapped is con-
trolled by Map-En[1:0] bits as shown in Table 3-1. The Map-
En[1:0] bits are the same bits as SFCF[1:0]. The Map-
En[1:0] bits are under software control and can be changed
during program execution. Since changing re-mapping will
cause program re-location, it is advisable that the instruction
that changes the Map-En[1:0] be in the portion of memory
that is not affected by the re-mapping change. (See Figures
3-4 and 3-5 and the application note, Memory Re-Mapping
of the SST89C54/58 Microcontroller).
The Map-En[1:0] bits are initialized at Reset according to
the contents of two non-volatile register bits, Re-Map[1:0].
The Re-Map[1:0] bits are programmed via PROG_RB1
and PROG_RB0 external host mode and IAP commands.
Refer to “External Host Programming Mode” in Section 4.1
or IAP section for description.
The contents of Map-En[1:0] are only updated according to
Re-Map[1:0] on a successful reset. Any subsequent alter-
ation to the Re-Map[1:0] bits will not automatically change
the Map-En[1:0] bits without a reset. Similarly, changes to
Map-En[1:0] during program execution will not change Re-
Map[1:0] bits.
To deactivate memory re-mapping, a Chip-Erase operation
will revert Re-Map[1:0] to the default status of “11”, dis-
abling re-map. Programming 00b to Map-En register also
deactivates memory re-mapping, during the run time.
TABLE 3-1: RE-MAPPING TABLE
RE-MAP[1:0]1 Map-En2,3 Comments
11 00 Re-mapping is turned off. Program memory is in normal configuration.
10 01 1 KByte of flash memory location is re-mapped.
Program access to location 0000H-03FFH is redirected to F000H-F3FFH.
01 10 2 KByte of flash memory location are re-mapped.
Program access to location 0000H-07FFH is redirected to F000H-F7FFH.
00 11 4 KByte of flash memory location is re-mapped.
Program access to location 0000H-0FFFH is redirected to F000H-FFFFH.
1. Map-En[1:0] are nonvolatile registers which are examined only during Reset.
2. Map-En[1:0] are initialized according to RE-MAP[1:0] during Reset.
3. Map-En[1:0] are located in SFCF[1:0], they determine the re-mapping configuration.
They may be changed by the program at run time.
T3-1.4 344
©2002 Silicon Storage Technology, Inc.
12
S71131-03-000 9/02 344

12 Page





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