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89C52 Schematic ( Datenblatt PDF ) - Integrated Silicon Solution Inc

Teilenummer 89C52
Beschreibung CMOS SINGLE CHIP 8-BIT MICROCONTROLLER with 8-Kbytes of FLASH
Hersteller Integrated Silicon Solution Inc
Logo Integrated Silicon Solution  Inc Logo 

Gesamt 30 Seiten
		
89C52 Datasheet, Funktion
IISS898C952C52
CMOS SINGLE CHIP
8-BIT MICROCONTROLLER
with 8-Kbytes of FLASH
ISSIISSI®®
NOVEMBER 1998
FEATURES
• 80C51 based architecture
• 8-Kbytes of on-chip Reprogrammable Flash
Memory
• 256 x 8 RAM
• Three 16-bit Timer/Counters
• Full duplex serial channel
• Boolean processor
• Four 8-bit I/O ports, 32 I/O lines
• Memory addressing capability
– 64K ROM and 64K RAM
• Program memory lock
– Lock bits (3)
• Power save modes:
– Idle and power-down
• Eight interrupt sources
• Most instructions execute in 0.3 µs
• CMOS and TTL compatible
• Maximum speed: 40 MHz @ Vcc = 5V
• Industrial temperature available
• Packages available:
– 40-pin DIP
– 44-pin PLCC
– 44-pin PQFP
GENERAL DESCRIPTION
The ISSI IS89C52 is a high-performance microcontroller
fabricated using high-density CMOS technology. The
CMOS IS89C52 is functionally compatible with the
industry standard 80C51 microcontrollers.
The IS89C52 is designed with 8-Kbytes of Flash
memory, 258 x 8 RAM; 32 programmable I/O lines; a serial
I/O port for either multiprocessor communications, I/O
expansion or full duplex UART; three 16-bit timer/counters;
an eight-source, two-priority-level, nested interrupt
structure; and an on-chip oscillator and clock circuit. The
IS89C52 can be expanded using standard TTL compatible
memory.
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RxD/P3.0
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2
XTAL1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA/VPP
30 ALE/PROG
29 PSEN
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
Figure 1. IS89C52 Pin Configuration: 40-pin PDIP
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC013-1C
11/21/98
1






89C52 Datasheet, Funktion
IS89C52
ISSI ®
Table 1. Detailed Pin Description (continued)
Symbol PDIP
P3.0-P3.7 10-17
PLCC
PQFP I/O
11, 13-19 5, 7-13 I/O
10 11
5I
11 13
7O
12 14
8I
13 15
9I
14 16 10 I
15 17 11 I
16 18 12 O
17 19 13 O
PSEN 29 32 26 O
RST
9 10 4 I
XTAL 1
19
21
15 I
XTAL 2
18
20
14 O
GND 20 22 16 I
Vcc 40 44 38 I
Name and Function
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal
pullups. Port 3 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally pulled low will source current
because of the internal pullups. (See DC Characteristics: IIL).
Port 3 also serves the special features of the IS89C52, as listed
below:
RxD (P3.0): Serial input port.
TxD (P3.1): Serial output port.
INT0 (P3.2): External interrupt 0.
INT1 (P3.3): External interrupt 1.
T0 (P3.4): Timer 0 external input.
T1 (P3.5): Timer 1 external input.
WR (P3.6): External data memory write strobe.
RD (P3.7): External data memory read strobe.
Program Store Enable: The read strobe to external program
memory. When the device is executing code from the external
program memory, PSEN is activated twice each machine cycle
except that two PSEN activations are skipped during each
access to external data memory. PSEN is not activated during
fetches from internal program memory.
Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device. An internal MOS resistor
to GND permits a power-on reset using only an external
capacitor connected to Vcc.
Crystal 1: Input to the inverting oscillator amplifier and input
to the internal clock generator circuits.
Crystal 2: Output from the inverting oscillator amplifier.
Ground: 0V reference.
Power Supply: This is the power supply voltage for operation.
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
MC013-1C
11/21/98

6 Page







89C52 pdf, datenblatt
IS89C52
ISSI ®
IP:
Interrupt Priority Register. Bit Addressable.
TCON:
Timer/Counter Control Register. Bit Addressable
7 6 5 4 3 2 10
— — — PS PT1 PX1 PT0 PX0
7 6 5 4 3 2 10
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Register Description:
— IP.7
— IP.6
Not implemented, reserve for future use(3)
Not implemented, reserve for future use(3)
— IP.5
Not implemented, reserve for future use(3)
PS IP.4
Defines Serial Port interrupt priority level
PT1 IP.3
Defines Timer 1 interrupt priority level
PX1 IP.2
Defines External Interrupt 1 priority level
PT0 IP.1
Defines Timer 0 interrupt priority level
PX0 IP.0
Defines External Interrupt 0 priority level
Notes:
1. In order to assign higher priority to an interrupt the
coresponding bit in the IP register must be set to 1. While
an interrupt service is in progress, it cannot be interrupted
by a lower or same level interrupt.
2. Priority within level is only to resolve simultaneous
requests of the same priority level. From high-to-low,
interrupt sources are listed below:
IE0
TF0
IE1
TF1
RI or TI
TF2 or EXF2
3. User software should not write 1s to reserved bits. These
bits may be used in future products to invoke new features.
Register Description:
TF1 TCON.7 Timer 1 overflow flag. Set by hardware
when the Timer/Counter 1 overflows.
Cleared by hardware as processor
vectors to the interrupt service routine.
TR1 TCON.6 Timer 1 run control bit. Set/Cleared by
software to turn Timer/Counter 1 ON/
OFF.
TF0 TCON.5 Timer 0 overflow flag. Set by hardware
when the Timer/Counter 0 overflows.
Cleared by hardware as processor
vectors to the interrupt service routine.
TR0 TCON.4 Timer 0 run control bit. Set/Cleared by
software to turn Timer/Counter 0 ON/
OFF.
IE1 TCON.3 External Interrupt 1 edge flag. Set by
hardware when the External Interrupt
edge is detected. Cleared by hardware
when interrupt is processed.
IT1 TCON.2 Interrupt 1 type control bit. Set/Cleared
by software specify falling edge/low level
triggered External Interrupt.
IE0 TCON.1 External Interrupt 0 edge flag. Set by
hardware when the External Interrupt
edge is detected. Cleared by hardware
when interrupt is processed.
IT0 TCON.0 Interrupt 0 type control bit. Set/Cleared
by software specify falling edge/low level
triggered External Interrupt.
12 Integrated Silicon Solution, Inc. — 1-800-379-4774
MC013-1C
11/21/98

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