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89C51RB2 Schematic ( Datenblatt PDF ) - NXP

Teilenummer 89C51RB2
Beschreibung 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
Hersteller NXP
Logo NXP Logo 

Gesamt 30 Seiten
		
89C51RB2 Datasheet, Funktion
INTEGRATED CIRCUITS
89C51RB2/89C51RC2/89C51RD2
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
Preliminary specification
IC28 Data Handbook
1999 Sep 23
Philips
Semiconductors






89C51RB2 Datasheet, Funktion
Philips Semiconductors
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
Preliminary specification
89C51RB2/89C51RC2/
89C51RD2
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
PDIP PLCC PQFP
VSS 20 22 16
VCC 40 44 38
P0.0–0.7
39–32 43–36 37–30
P1.0–P1.7
1–8
2–9 40–44,
1–3
P2.0–P2.7
1
2
3
4
5
6
7
8
21–28
2
3
4
5
6
7
8
9
24–31
40
41
42
43
44
1
2
3
18–25
P3.0–P3.7
10–17
11, 5, 7–13
13–19
RST
ALE
10 11
5
11 13
7
12 14
8
13 15
9
14 16 10
15 17 11
16 18 12
17 19 13
9 10 4
30 33 27
TYPE
NAME AND FUNCTION
I Ground: 0 V reference.
I Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during accesses to external program
and data memory. In this application, it uses strong internal pull-ups when emitting 1s.
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins
except P1.6 and P1.7 which are open drain. Port 1 pins that have 1s written to them
are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1
pins that are externally pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: IIL).
Alternate functions for 89C51RB2/RC2/RD2 Port 1 include:
I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout (see Programmable
Clock-Out)
I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
I ECI (P1.2): External Clock Input to the PCA
I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0
I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1
I/O CEX2 (P1.5): Capture/Compare External I/O for PCA module 2
I/O CEX3 (P1.6): Capture/Compare External I/O for PCA module 3
I/O CEX4 (P1.7): Capture/Compare External I/O for PCA module 4
I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 2 pins that are externally being pulled low will source current
because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2
emits the high-order address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s.
During accesses to external data memory that use 8-bit addresses (MOV @Ri),
port 2 emits the contents of the P2 special function register.
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 3 pins that are externally being pulled low will source current
because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves
the special features of the 89C51RB2/RC2/RD2, as listed below:
I RxD (P3.0): Serial input port
O TxD (P3.1): Serial output port
I INT0 (P3.2): External interrupt
I INT1 (P3.3): External interrupt
I T0 (P3.4): Timer 0 external input
I T1 (P3.5): Timer 1 external input
O WR (P3.6): External data memory write strobe
O RD (P3.7): External data memory read strobe
I Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to VSS permits a power-on reset
using only an external capacitor to VCC.
O Address Latch Enable: Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted twice
every machine cycle, and can be used for external timing or clocking. Note that one
ALE pulse is skipped during each access to external data memory. ALE can be
disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a
MOVX instruction.
1999 Sep 23
6

6 Page







89C51RB2 pdf, datenblatt
Philips Semiconductors
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
Preliminary specification
89C51RB2/89C51RC2/
89C51RD2
Table 3. Timer 2 Operating Modes
RCLK + TCLK
CP/RL2
00
01
1X
XX
TR2 MODE
1 16-bit Auto-reload
1 16-bit Capture
1 Baud rate generator
0 (off)
OSC
÷ n*
T2 Pin
C/T2 = 0
C/T2 = 1
Transition
Detector
Control
TR2 Capture
TL2
(8-bits)
TH2
(8-bits)
RCAP2L
RCAP2H
TF2
Timer 2
Interrupt
T2EX Pin
Control
EXEN2
* n = 6 in 6 clock mode, or 12 in 12 clock mode.
Figure 2. Timer 2 in Capture Mode
EXF2
SU01252
T2MOD Address = 0C9H
Reset Value = XXXX XX00B
Not Bit Addressable
— — — — — — T2OE DCEN
Bit 7 6 5 4 3 2 1 0
Symbol Function
T2OE
DCEN
Not implemented, reserved for future use.*
Timer 2 Output Enable bit.
Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.
In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
SU00729
Figure 3. Timer 2 Mode (T2MOD) Control Register
1999 Sep 23
12

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