Datenblatt-pdf.com


8840 Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer 8840
Beschreibung In-System Programmable SuperBIG High Density PLD
Hersteller Lattice Semiconductor
Logo Lattice Semiconductor Logo 




Gesamt 23 Seiten
8840 Datasheet, Funktion
ispLSI® 8840
In-System Programmable
SuperBIG™ High Density PLD
Features
• SuperBIG HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 5V Power Supply
— 45,000 PLD Gates/840 Macrocells
— Up to 312 I/O Pins Supporting 3.3V/5V I/O
— 1152 Registers
— High-Speed Global and Big Fast Megablock (BFM)
Interconnect
— Wide 20-Macrocell Generic Logic Block (GLB) for
High Performance
— Wide Input Gating (44 Inputs per GLB) for Fast
Counters, State Machines, Address Decoders, Etc.
— PCB-Efficient Ball Grid Array (BGA) Package
Options
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 110 MHz Maximum Operating Frequency
tpd = 8.5 ns Propagation Delay
— TTL Compatible Inputs and 3.3V/5V Outputs
— PCI Compatible Inputs, Outputs and Speed Grades
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
5V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture, Symmetrical
Generic Logic Blocks Connected by Hierarchical
Big Fast Megablock and Global Routing Planes
— Product Term Sharing Array Supports up to 28
Product Terms per Macrocell Output
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Embedded Tristate Bus Can Be Used as an Internal
Tristate Bus or as an Extension of an External
Tristate Bus
— Macrocell and I/O Registers Feature Multiple Control
Options, Including Set, Reset and Clock Enable
— I/O Pins Support Programmable Bus Hold, Pull-Up,
Open-Drain and Slew Rate Options
— Separate VCCIO Power Supply for Output Drivers
Supports 5V or 3.3V Outputs
— I/O Cell Register Programmable as Input Register for
Fast Setup Time or Output Register for Fast Clock to
Output Time
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
12 12 12 12 12 12
I/O I/O I/O I/O I/O I/O
12
I/O
Big Fast Megablock 0
12
I/O
12
I/O
Big Fast Megablock 1
12
I/O
12
I/O
Big Fast Megablock 2
Global Routing Plane
12
I/O
Big Fast Megablock 3
12
I/O
12
I/O
12
I/O
Big Fast Megablock 4
12
I/O
12
I/O
Big Fast Megablock 5
12
I/O
12
I/O
Big Fast Megablock 6
12
I/O
Boundary
Scan
12 12 12 12 12 12
I/O I/O I/O I/O I/O I/O
8840 block
ispLSI 8000 Family Description
The ispLSI 8000 Family of Register-Intensive, SuperBIG
In-System Programmable Logic Devices is based on Big
Fast Megablocks of 120 registered macrocells and a
Global Routing Plane (GRP) structure interconnecting
the Big Fast Megablocks. Each Big Fast Megablock
contains 120 registered macrocells arranged in six groups
of 20, a group of 20 being referred to as a Generic Logic
Block, or GLB. Within the Big Fast Megablock, a Big Fast
Megablock Routing Pool (BRP) interconnects the six
GLBs to each other and to 24 Big Fast Megablock I/O
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
January 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
8840_07
1






8840 Datasheet, Funktion
Figure 3. ispLSI 8000 Macrocell Overview
Specifications ispLSI 8840
Single PT
PTSA
PTSA Bypass
PT Clock
Global Clock Enable
Global Clock 0
Global Clock 1
Global Clock 2
PT Reset
GRST
PT Preset
Reset pin
GRST
Preset/Reset Input has Global Polarity Control
*Not available for Macrocells 9 and 10.
DQ
Clk En
R/L
RP
Bus Input From Tristate
Bus Track*
Feedback to AND Array
To Big Fast Megablock
or Global Interconnect
To Specific
Global Tristate Bus*
From Macrocell
9 or 10
Macrocells 0-8
and 11-19
From PT80
To All Macrocells and I/O Cells
: Function Selector (E2 Cell Controlled)
6

6 Page









8840 pdf, datenblatt
Specifications ispLSI 8840
Switching Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Time
1.5 ns 10% to 90%
Input Timing Reference Levels
1.5V
Ouput Timing Reference Levels
1.5V
Output Load
3-state levels are measured 0.5V from
steady-state active level.
See Figure 2
Table 2-0003/8840
Output Load Conditions (See Figure 9)
Figure 9. Test Load
+ 5V (VCC and VCCIO)
Device
Output
R1
Test
Point
R2 CL*
TEST CONDITION
A
Active High
B
Active Low
Active High to Z
C at VOH -0.5V
Active Low to Z
at VOL+0.5V
R1
470
470
470
DC Electrical Characteristics
R2
390
390
390
390
CL
35pF
35pF
35pF
5pF
3905pF
Table 2-0004A/8840
*CL includes Test Fixture and Probe Capacitance.
0213A/8840
Over Recommended Operating Conditions
SYMBOL
PARAMETER
CONDITION
MIN. TYP.3 MAX. UNITS
VOL
VOH
IIL
IIH
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
IOL = 8 mA
IOH = -4 mA
0.0V VIN0.8V
3.5V VIN VCC
VCCIO = 5V
(VCCIO - 0.2) VIN VCCIO
VCCIO = 3.3V
VCCIO < VIN 5.25V
VIN >VCCIO
– – 0.4 V
2.4 – – V
– – -10 µA
– – 10 µA
– – 10 µA
– – 10 µA
IPU Active Pullup Current, Input or I/O 0V VIN 2.0V
-10 -250 µA
IBHL
IBHH
Bus-Hold Low Sustaining Current
Bus-Hold High Sustaining Current
VIN = 0.8V
VIN = 2.0V
50
-50
µA
µA
IBHLO
IBHHO
Bus-Hold Low, Overdrive Current
Bus-Hold High, Overdrive Current
0V VIN VCCIO
0V VIN VCCIO
– – 550 µA
– – -550 µA
VBHT
IOS 1
Bus-Hold Trip Point (1.4V Nominal)
Output Short Circuit Current
VCC = 5V, VOUT = 0.5V
0.8 2.0 V
– – -200 mA
ICC 2,4
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V High Speed Mode
630
mA
fCLOCK = 1MHz
Low Power Mode 340 mA
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using 42 20-bit counters.
3. Typical values are at VCC= 5V and TA= 25°C.
4. Maximum ICC varies widely with specific device configuration and operating frequency.
Table 2-0007/8840
12

12 Page





SeitenGesamt 23 Seiten
PDF Download[ 8840 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
8840In-System Programmable SuperBIG High Density PLDLattice Semiconductor
Lattice Semiconductor
8841-N2TDA8841-N2NXP Semiconductors
NXP Semiconductors

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche