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87C196KQ Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer 87C196KQ
Beschreibung ADVANCED 16-BIT CHMOS MICROCONTROLLER
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 25 Seiten
87C196KQ Datasheet, Funktion
87C196KR KQ 87C196JV JT 87C196JR JQ
ADVANCED 16-BIT CHMOS MICROCONTROLLER
Automotive
Y b40 C to a125 C Ambient
Y High Performance CHMOS 16-Bit CPU
Y Up to 48 Kbytes of On-Chip EPROM
Y Up to 1 5 Kbytes of On-Chip Register
RAM
Y Up to 512 Bytes of Additional RAM
(Code RAM)
Y Register-Register Architecture
Y Up to 8 Channel 10-Bit A D with
Sample Hold
Y Up to 37 Prioritized Interrupt Sources
Y Up to Seven 8-Bit (56) I O Ports
Y Full Duplex Serial I O Port
Y Dedicated Baud Rate Generator
Y Interprocessor Communication Slave
Port
Y High Speed Peripheral Transaction
Server (PTS)
Y Two 16-Bit Software Timers
Y 10 High Speed Capture Compare (EPA)
Y Full Duplex Synchronous Serial I O
Port (SSIO)
Y Two Flexible 16-Bit Timer Counters
Y Quadrature Counting Inputs
Y Flexible 8- 16-Bit External Bus
Y Programmable Bus (HLD HLDA)
Y 1 75 ms 16 x 16 Multiply
Y 3 ms 32 16 Divide
Y 68-Pin and 52-Pin PLCC Packages
Device Pins Package EPROM Reg RAM Code RAM I O EPA SIO SSIO A D
87C196KR 68-pin PLCC
16K
488
256 56 10 Y Y 8
87C196KQ 68-pin PLCC
12K
360
128 56 10 Y Y 8
87C196JV 52-pin PLCC 48K 1 5K
512
41 6
Y
Y
6
87C196JT 52-pin PLCC 32K 1 0K
512
41 6
Y
Y
6
87C196JR 52-pin PLCC
16K
488
256
41 6
Y
Y
6
87C196JQ 52-pin PLCC
12K
360
128
41 6
Y
Y
6
The 87C196KR KQ JV JT JR JQ devices represent the fourth generation of MCS 96 Microcontroller prod-
ucts implemented on Intel’s advanced 1 micron process technology These products are based on the
80C196KB device with improvements for automotive applications The instruction set is a true super set of
80C196KB The 87C196JR is a 52-pin version of the 87C196KR device while the 87C196KQ JQ are memory
scalars of the 87C196KR JR
The 87C196JV JT A-step devices (JV-A JT-A) are the newest members of the MCS 96 microcontroller family
These devices are memory scalars of the 87C196JR D-step (JR-D) and are designed for strict functional and
electrical compatibility The JT-A has 32 Kbytes of on-chip EPROM 1 0 Kbytes of Register RAM and 512
bytes of Code RAM The JV-A has 48 Kbytes of on-chip EPROM 1 5 Kbytes of Register RAM and 512 bytes
of Code RAM
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 270827-006






87C196KQ Datasheet, Funktion
87C196KR KQ 87C196JV JT 87C196JR JQ
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
P5 3 RD
Read signal output to external memory RD is active only during external memory
reads or LSIO when not used as RD
P5 2 WR WRL
Write and Write Low output to external memory as selected by the CCR WR will
go low for every external write while WRL will go low only for external writes
where an even byte is being written WR WRL is active during external memory
writes Also an LSIO pin when not used as WR WRL
P5 5 BHE WRH
Byte High Enable or Write High output as selected by the CCR BHE e 0 selects
the bank of memory that is connected to the high byte of the data bus A0 e 0
selects that bank of memory that is connectd to the low byte Thus accesses to a
16-bit wide memory can be to the low byte only (A0 e 0 BHE e 1) to the high
byte only (A0 e 1 BHE e 0) or both bytes (A0 e 0 BHE e 0) If the WRH
function is selected the pin will go low if the bus cycle is writing to an odd memory
location BHE WRH is only valid during 16-bit external memory write cycles Also
an LSIO pin when not BHE WRH
P5 6 READY
Ready input to lengthen external memory cycles for interfacing with slow or
dynamic memory or for bus sharing If the pin is high CPU operation continues in
a normal manner If the pin is low prior to the falling edge of CLKOUT the memory
controller goes into a wait state mode until the next positive transition in CLKOUT
occurs with READY high When external memory is not used READY has no
effect The max number of wait states inserted into the bus cycle is controlled by
the CCR CCR1 Also an LSIO pin when READY is not selected
P5 4 SLPINT
Dual functional I O pin As a bidirectional port pin or as a system function The
system function is a Slave Port Interrupt Output Pin
P6 2 T1CLK
Dual function I O pin Primary function is that of a bidirectional I O pin however it
may also be used as a TIMER1 Clock input The TIMER1 will increment or
decrement on both positive and negative edges of this pin
P6 3 T1DIR
Dual function I Opin Primary function is that of a bidirectional I O pin however it
may also be used as a TIMER1 Direction input The TIMER1 will increment when
this pin is high and decrements when this pin is low
PORT1 EPA0–7
P6 0–6 1 EPA8–9
Dual function I O port pins Primary function is that of bidirectional I O System
function is that of High Speed capture and compare EPA0 and EPA2 have yet
another function of T2CLK and T2DIR of the TIMER2 timer counter
PORT 0 ACH0–7
8-bit high impedance input-only port These pins can be used as digital inputs
and or as analog inputs to the on-chip A D converter These pins are also used
as inputs to EPROM parts to select the Programming Mode
P6 4–6 7 SSIO
Dual function I O ports that have a system function as Synchronous Serial I O
Two pins are clocks and two pins are data providing full duplex capability
PORT 2
8-bit multi-functional port All of its pins are shared with other functions
PORT 3 and 4
8-bit bidirectional I O ports with open drain outputs These pins are shared with
the multiplexed address data bus which has strong internal pullups
6

6 Page









87C196KQ pdf, datenblatt
87C196KR KQ 87C196JV JT 87C196JR JQ
System Bus Timing
READY BUSWIDTH TIMING
12
270827 – 5
270827 – 6

12 Page





SeitenGesamt 25 Seiten
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