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8600V Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer 8600V
Beschreibung 3.3V In-System Programmable SuperBIG High Density PLD
Hersteller Lattice Semiconductor
Logo Lattice Semiconductor Logo 




Gesamt 26 Seiten
8600V Datasheet, Funktion
ispLSI® 8600V
3.3V In-System Programmable
SuperBIG™ High Density PLD
Features
• SuperBIG HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 3.3V Power Supply
— 32,000 PLD Gates/600 Macrocells
— 192-264 I/O Pins Supporting 3.3V/2.5V I/O
— 864 Registers
— High-Speed Global and Big Fast Megablock (BFM)
Interconnect
— Wide 20-Macrocell Generic Logic Block (GLB) for
High Performance
— Wide Input Gating (44 Inputs per GLB) for Fast
Counters, State Machines, Address Decoders, Etc.
— PCB-Efficient Ball Grid Array (BGA) Package
Options
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 125 MHz Maximum Operating Frequency
tpd = 8.5 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture, Symmetrical
Generic Logic Blocks Connected by Hierarchical
Big Fast Megablock and Global Routing Planes
— Product Term Sharing Array Supports up to 28
Product Terms per Macrocell Output
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Embedded Tristate Bus Can Be Used as an Internal
Tristate Bus or as an Extension of an External
Tristate Bus
— Macrocell and I/O Registers Feature Multiple Control
Options, Including Set, Reset and Clock Enable
— I/O Pins Support Programmable Bus Hold, Pull-Up,
Open-Drain and Slew Rate Options
— Separate VCCIO Power Supply to Support 3.3V or
2.5V Input/Output Logic Levels
— I/O Cell Register Programmable as Input Register for
Fast Setup Time or Output Register for Fast Clock to
Output Time
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
12 12 12 12 12 12
I/O I/O I/O I/O I/O I/O
12
I/O
Big Fast Megablock 0
12
I/O
12
I/O
Big Fast Megablock 1
12
I/O
12
I/O
Big Fast Megablock 2
Global Routing Plane
12
I/O
Big Fast Megablock 3
12
I/O
12
I/O
12
I/O
Big Fast Megablock 4
12
I/O
Boundary
Scan
12 12 12 12 12 12
I/O I/O I/O I/O I/O I/O
8600v block
ispLSI 8000V Family Description
The ispLSI 8000V Family of Register-Intensive, 3.3V
SuperBIG In-System Programmable Logic Devices is
based on Big Fast Megablocks of 120 registered macro-
cells and a Global Routing Plane (GRP) structure
interconnecting the Big Fast Megablocks. Each Big Fast
Megablock contains 120 registered macrocells arranged
in six groups of 20, a group of 20 being referred to as a
Generic Logic Block, or GLB. Within the Big Fast
Megablock, a Big Fast Megablock Routing Pool (BRP)
interconnects the six GLBs to each other and to 24 Big
Fast Megablock I/O cells with optional I/O registers. The
Global Routing Plane which interconnects the Big Fast
Megablocks has additional global I/Os with optional I/O
registers. The 192-I/O version contains 72 Big Fast
Megablock I/O and 120 global I/O, while the 264-I/O
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
July 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
8600v_03
1






8600V Datasheet, Funktion
Specifications ispLSI 8600V
Figure 3. ispLSI 8000V Macrocell Overview
Single PT
PTSA
PTSA Bypass
PT Clock
Global Clock Enable
Global Clock 0
Global Clock 1
Global Clock 2
PT Reset
GRST
PT Preset
Reset pin
GRST
Preset/Reset Input has Global Polarity Control
*Not available for Macrocells 9 and 10.
From PT80
DQ
Clk En
R/L
RP
Bus Input From Tristate
Bus Track*
Feedback to AND Array
To Big Fast Megablock
or Global Interconnect
To Specific
Global Tristate Bus*
From Macrocell
9 or 10
To All Macrocells and I/O Cells
: Function Selector (E2 Cell Controlled)
6

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8600V pdf, datenblatt
Specifications ispLSI 8600V
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
GND to VCCIOmin
1.5 ns 10% to 90%
Input Timing Reference Levels
1.5V
Ouput Timing Reference Levels
1.5V
Output Load
3-state levels are measured 0.5V from
steady-state active level.
See Figure 9
Table 2-0003/8600V
Output Load Conditions (See Figure 9)
Figure 9. Test Load
VCCIO
Device
Output
R1
R2
Test
Point
CL*
3.3V
2.5V
TEST CONDITION
R1 R2 R1 R2 CL
A 31634851147535pF
Active High
B
Active Low
348Ω ∞ 47535pF
316Ω ∞ 511Ω ∞ 35pF
C
Active High to Z
at VOH -0.5V
348Ω ∞ 4755pF
Active Low to Z
at VOL+0.5V
316
511
5pF
D Slow Slew
∞ ∞ ∞ ∞ 35pF
Table 2-0004A/8600V
*CL includes Test Fixture and Probe Capacitance.
0213A/8600V
DC Electrical Characteristics for 3.3V Range
Over Recommended Operating Conditions
SYMBOL
PARAMETER
VCCIO I/O Supply Voltage
VIL Input Low Voltage
VIH Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
CONDITION
TA = 0°C to + 70°C
IOL = 8 mA
IOH = -4 mA
DC Electrical Characteristics for 2.5V Range
Over Recommended Operating Conditions
SYMBOL
PARAMETER
VCCIO I/O Supply Voltage
VIL Input Low Voltage
VIH Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
CONDITION
TA = 0°C to + 70°C
VCCIO=min, VIN=VIH or VIL, IOL= 100µA
VCCIO=min, VIN=VIH or VIL, IOL= 2mA
VCCIO=min, VIN=VIH or VIL, IOH= -100µA
VCCIO=min, VIN=VIH or VIL, IOH= -2mA
MIN.
3.0
-0.3
2.0
2.4
MAX. UNITS
3.6 V
0.8 V
5.25 V
0.4 V
V
Table 2-0007/8600V
MIN.
2.3
-0.3
1.7
2.1
1.7
MAX. UNITS
2.7 V
0.7 V
5.25 V
0.2 V
0.7 V
V
V
Table 2-0007B/8600V
12

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