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84C443 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer 84C443
Beschreibung 8-bit microcontrollers with OSD and VST
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 40 Seiten
84C443 Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
84C44X; 84C64X; 84C84X
8-bit microcontrollers with
OSD and VST
Product specification
Supersedes data of October 1994
File under Integrated Circuits, IC14
1996 Nov 29






84C443 Datasheet, Funktion
Table 1 Pin description
SYMBOL(1)
PIN(1)
84CX40; 84CX43 84CX41; 84CX44 84CX40; 84CX43 84CX41; 84CX44
DESCRIPTION
Deviating pinning
DP1.0 to DP1.4 DP1.0 to DP1.3
T1 T1
DOSC1
DOSC1/DOSC2
41, 38, 37, 36, 34 41, 38, 37, 36
29 34
28
28, 29
Derivative Port 1: quasi-bidirectional I/O lines.
Direct testable pin and event counter input.
Connection to RC oscillator of OSD clock.
Connections to LC oscillator of OSD clock.
Mutual pinning
DP0.0/TDAC
DP0.1 to DP0.5/PWM1 to PWM5
P1.0 to P1.4
P0.0 to P0.7
DP1.7/AFC
DP0.6/SDA
DP0.7/SCL
INT/T0
DP1.5 and DP1.6/VOW2 and VOW1
RESET
XTAL2, XTAL1
TEST/EMU
VSYNCN
HSYNCN
VOB
VOW3
VSS
VDD
1
2 to 6
7, 8, 10, 11 and 12
13 to 20
9
40
39
35
23, 22
33
32, 31
30
27
26
25
24
21
42
Derivative Port 0: quasi-bidirectional I/O line or 14-bit DAC PWM.
Derivative Port 1: quasi-bidirectional I/O lines or 6-bit DAC PWM.
Port 1: quasi-bidirectional I/O lines.
Port 0: quasi-bidirectional I/O port.
Derivative Port 1:
quasi-bidirectional I/O line or comparator input with 3-bit DAC.
Derivative open drain I/O port or I2C-bus data line.
Derivative open drain I/O port or I2C- bus clock line.
External interrupt or direct testable line.
Derivative Port 1:
quasi-bidirectional I/O lines or character video output.
Initialize input, active LOW.
Oscillator output or input terminal for system clock.
Control input for testing and emulation mode. Ground for normal
operation.
Vertical synchronous signal input.
Horizontal synchronous signal input.
Blanking output.
Character video output of OSD.
Ground.
Power supply.
Note
1. 84CX40; 84CX43 denotes the types: PCA84C440, PCA84C443, PCA84C640, PCA84C643, PCA84C840 and PCA84C843.
84CX41; 84CX44 denotes the types: PCA84C441, PCA84C444, PCA84C641, PCA84C644, PCA84C841 and PCA84C844.

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84C443 pdf, datenblatt
Philips Semiconductors
8-bit microcontrollers with OSD and VST
Product specification
84C44X; 84C64X; 84C84X
9 VST CONTROL
9.1 14-bit PWM DAC
The PCA84C640 has one 14-bit PWM DAC output (TDAC)
with a resolution of 16384 levels for Voltage Synthesized
Tuning. The PWM DAC (see Fig.10) consists of:
14-bit counter
Two 7-bit DAC interface data latches (VSTH and VSTL)
One 14-bit DAC data latch (VSTREG)
Pulse control.
The polarity of output TDAC is selected with bit P14LVL.
Setting the bit P14LVL to:
Logic 1, sets the TDAC output to the default polarity
Logic 0, inverts the TDAC output.
9.1.1 14-BIT COUNTER
The counter is continuously running and is clocked by f0.
The period of the clock, t0 = f--X----T3---A---L-
The repetition time for one complete cycle of the counter:
tr = t0 × 16 384
The repetition time for one cycle of the lower 7-bits of the
counter is:
tsub = t0 × 128
Therefore, the number of tsub periods in a complete
cycle tr is:
N = -t-0--t--0×----×-1----61---2-3---88---4-- = 128
9.1.2 DATA AND INTERFACE LATCHES
In order to ensure correct operation, interface data latch
VSTH is loaded first and then interface data latch VSTL.
The contents of:
VSTH are used for coarse adjustment
VSTL are used for fine adjustment.
At the beginning of the first tsub period following the loading
of VSTL, both data latches are loaded into data latch
VSTREG. After the contents of VSTH and VSTL are
latched into VSTREG, one tsub period is needed to
generate the appropriate pulse pattern.
To ensure correct DAC conversion, two (2) tsub periods
should be allowed before beginning the next sequence.
9.2 Coarse adjustment
The coarse adjustment output (OUT1) is reset to LOW
(inactive) at the start of each tsub period.
It will remain LOW until the time [t0 × (VSTH + 1) ] has
elapsed and then will go HIGH and remain so until the next
tsub period starts.
9.3 Fine adjustment
Fine adjustment is achieved by generating additional
pulses at the start of particular sub-periods (tsubn).
These additional pulses have a width of t0.
The sub-period in which a pulse is added is determined by
the contents of VSTL interface latch.
Table 3 gives the numbers of the tsubn, at the start of which
an additional pulse is generated, depending on the bit in
VSTL being a logic 0. When more than one bit is a logic 0
a combination of additional pulses are generated.
For example, if VSTL = 1111010, which is a combination
of
VSTL = 1111110: sub-period 64, and
VSTL = 1111011: sub-periods 16, 48, 80 and 112,
then additional pulses will be given in sub-periods
16, 48, 64, 80 and 112; this is illustrated in Fig.12.
If VSTH = 0011101, VSTL = 1111010 and P14LVL = 0,
then the TDAC output is as shown in Fig.13.
Table 3 Additional pulse distribution
LOWER
7 BITS
(VSTL)
111 1110
111 1101
111 1011
111 0111
110 1111
101 1111
011 1111
ADDITIONAL PULSE IN
SUB-PERIODS tsubn
64
32, 96
16, 48, 80, 112
8, 24, 40, 56, 72, 88, 104, 120
4, 12, 20, 28, 36, 44, 52, 60 .... 116, 124
2, 6, 10, 14, 18, 22, 26, 30, .... 122, 126
1, 3, 5, 7, 9, 11, 13, 15, 17, .... 125, 127
1996 Nov 29
12

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