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84069012A Schematic ( Datenblatt PDF ) - Intersil Corporation

Teilenummer 84069012A
Beschreibung CMOS Bus Controller
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 

Gesamt 10 Seiten
		
84069012A Datasheet, Funktion
82C88
March 1997
CMOS Bus Controller
Features
Description
• Compatible with Bipolar 8288
• Performance Compatible with:
- 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz)
- 80186/80188 . . . . . . . . . . . . . . . . . . . . . . . . . .(6/8MHz)
- 8086/8088 . . . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz)
- 8089
• Provides Advanced Commands for Multi-Master
Busses
• Three-State Command Outputs
• Bipolar Drive Capability
• Scaled SAJI IV CMOS Process
• Single 5V Power Supply
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA (Max)
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . .1mA/MHz (Max)
• Operating Temperature Ranges
- C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C88 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 82C88 is a high performance CMOS Bus Con-
troller manufactured using a self-aligned silicon gate CMOS
process (Scaled SAJI IV). The 82C88 provides the control
and command timing signals for 80C86, 80C88, 8086, 8088,
8089, 80186, and 80188 based systems. The high output
drive capability of the 82C88 eliminates the need for addi-
tional bus drivers.
Static CMOS circuit design insures low operating power. The
Intersil advanced SAJI process results in performance equal
to or greater than existing equivalent products at a significant
power savings.
Ordering Information
PART NUMBER
CP82C88
CP82C88-10
IP82C88
CS82C88
IS82C88
CD82C88
ID82C88
MD82C88/B
8406901RA
MR82C88/B
84069012A
PACKAGE
20 Ld PDIP
20 Ld
PLCC
20 Ld
CERDIP
SMD#
20 Pad
CLCC
SMD#
TEMPERATURE
RANGE
0oC to +70oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PKG.
NO.
E20.3
E20.3
E20.3
N20.35
N20.35
F20.3
F20.3
F20.3
F20.3
J20.A
J20.A
Pinouts
20 LEAD PDIP, CERDIP
TOP VIEW
IOB 1
CLK 2
S1 3
DT/ R 4
ALE 5
AEN 6
MRDC 7
AMWC 8
MWTC 9
GND 10
20 VCC
19 S0
18 S2
17 MCE/PDEN
16 DEN
15 CEN
14 INTA
13 IORC
12 AIOWC
11 IOWC
20 LEAD PLCC, CLCC
TOP VIEW
3 2 1 20 19
DT/ R 4
ALE 5
AEN 6
18 S2
17 MCE/PDEN
16 DEN
MRDC 7
15 CEN
AMWC 8
14 INTA
9 10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-333
File Number 2979.1






84069012A Datasheet, Funktion
82C88
AC Electrical Specifications
VCC = 5.0V ± 10%;
TA
TA
TA
=
=
=
0oC to +70oC (C82C88);
-40oC to +85oC (I82C88);
-55oC to +125oC (M82C88)
8MHz
10MHz
SYMBOL
PARAMETER
MIN MAX MIN MAX
TIMING REQUIREMENTS
(1) TCLCL CLK Cycle Period
125 - 100 -
(2) TCLCH CLK Low Time
55 - 50 -
(3) TCHCL CLK High Time
40 - 37 -
(4) TSVCH Status Active Setup Time
35 - 35 -
(5) TCHSV Status Inactive Hold Time
10 - 10 -
(6) TSHCL Status Inactive Setup Time
35 - 35 -
(7) TCLSH Status Active Hold Time
10 - 10 -
TIMING RESPONSES
(8) TCVNV Control Active Delay
5 45 5 45
(9) TCVNX Control Inactive Delay
10 45 10 45
(10) TCLLH ALE Active Delay (from CLK) - 20 - 20
(11) TCLMCH MCE Active Delay (from CLK)
-
25
-
23
(12) TSVLH ALE Active Delay (from Status)
-
20
-
20
(13) TSVMCH MCE Active Delay (from Status)
-
30
-
23
(14) TCHLL ALE Inactive Delay
4 18 4 18
(15) TCLML Command Active Delay
5 35 5 35
(16) TCLMH Command Inactive Delay
5 35 5 35
(17) TCHDTL Direction Control Active Delay
-
50
-
50
(18) TCHDTH Direction Control Inactive Delay
-
30
-
30
(19) TAELCH Command Enable Time (Note 1) - 40 - 40
(20) TAEHCZ Command Disable Time
(Note 2)
- 40 - 40
(21) TAELCV Enable Delay Time
110 250 110 250
(22) TAEVNV AEN to DEN
- 25 - 25
(23) TCEVNV CEN to DEN, PDEN
- 25 - 25
(24) TCELRH CEN to Command
- TCLML - TCLML
+10
(25) TLHLL ALE High Time
TCLCH - - TCLCH - -
10 10
NOTES:
1. TAELCH measurement is between 1.5V and 2.5V.
2. TAEHCZ measured at 0.5V change in VOUT.
12MHz
MIN MAX
83 -
34 -
34 -
35 -
5-
35 -
5-
5 45
10 35
- 20
- 23
- 20
- 23
4 18
5 35
5 35
- 50
- 30
- 40
- 40
110 250
- 25
- 25
- TCLML
TCLCH -
10
n
TEST
UNITS CONDITIONS
ns
ns
ns
ns
ns
ns
ns
ns 1
ns 1
ns 1
ns 1
ns 1
ns 1
ns 1
ns 2
ns 2
ns 1
ns 1
ns 3
ns 4
ns 2
ns 1
ns 1
ns 2
ns 1
AC Testing Input, Output Waveform
INPUT
VIH +0.4V
1.5V
VIL -0.4V
OUTPUT
VOH
1.5V
VOL
A.C. Testing: All input signals (other than CLK) must switch
between VIL -0.4V and VIH +0.4. CLK must switch between 0.4V
and VCC -0.4V. Input rise and fall times are driven at 1ns/V.
A.C. Test Circuit
V1
OUTPUT FROM
DEVICE
UNDER TEST
NOTE:
INCLUDES STRAY AND JIG CAPACITANCE
R1
TEST
POINT
C1 (SEE NOTE)
TABLE 2. TEST CONDITION DEFINITION TABLE
TEST CONDITION
1
2
3
4
V1
2.13V
2.29V
1.5V
1.5V
R1
220
91
187
187
C1
80pF
300pF
300pF
50pF
4-338

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