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84068012A Schematic ( Datenblatt PDF ) - Intersil Corporation

Teilenummer 84068012A
Beschreibung CMOS Clock Generator Driver
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 

Gesamt 10 Seiten
		
84068012A Datasheet, Funktion
82C84A
March 1997
CMOS Clock Generator Driver
Features
Description
• Generates the System Clock For CMOS or NMOS
Microprocessors
• Up to 25MHz Operation
• Uses a Parallel Mode Crystal Circuit or External
Frequency Source
• Provides Ready Synchronization
• Generates System Reset Output From Schmitt Trigger
Input
• TTL Compatible Inputs/Outputs
• Very Low Power Consumption
• Single 5V Power Supply
• Operating Temperature Ranges
- C82C84A . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C84A . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C84A . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 82C84A is a high performance CMOS Clock Generator-
driver which is designed to service the requirements of both CMOS
and NMOS microprocessors such as the 80C86, 80C88, 8086 and
the 8088. The chip contains a crystal controlled oscillator, a divide-by-
three counter and complete “Ready” synchronization and reset logic.
Static CMOS circuit design permits operation with an external fre-
quency source from DC to 25MHz. Crystal controlled operation to
25MHz is guaranteed with the use of a parallel, fundamental mode
crystal and two small load capacitors.
All inputs (except X1 and RES) are TTL compatible over tempera-
ture and voltage ranges.
Power consumption is a fraction of that of the equivalent bipolar cir-
cuits. This speed-power characteristic of CMOS permits the
designer to custom tailor his system design with respect to power
and/or speed requirements.
Ordering Information
PART
NUMBER
CP82C84A
IP82C84A
CS82C84A
IS82C84A
CD82C84A
ID82C84A
MD82C84A/B
8406801VA
MR82C84A/B
84068012A
TEMP. RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PACKAGE
PKG.
NO.
18 Ld PDIP E18.3
E18.3
20 Ld PLCC N20.35
N20.35
18 Ld CERDIP F18.3
F18.3
F18.3
SMD#
F18.3
20 Pad CLCC J20.A
SMD#
J20.A
Pinouts
82C84A (PDIP, CERDIP)
TOP VIEW
CSYNC 1
PCLK 2
AEN1 3
RDY1 4
READY 5
RDY2 6
AEN2 7
CLK 8
GND 9
18 VCC
17 X1
16 X2
15 ASYNC
14 EFI
13 F/C
12 OSC
11 RES
10 RESET
82C84A (PLCC, CLCC)
TOP VIEW
3 2 1 20 19
RDY1 4
READY 5
RDY2 6
AEN2 7
NC 8
18 X2
17 ASYNC
16 EFI
15 F/C
14 NC
9 10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-287
File Number 2974.1






84068012A Datasheet, Funktion
82C84A
AC Electrical Specifications
VCC = +5V± 10%,
TA = 0oC to +70oC (C82C84A),
TA = -40oC to +85oC (I82C84A),
TA = -55oC to +125oC (M82C84A)
SYMBOL
PARAMETER
LIMITS
MIN
MAX
UNITS
(NOTE 1)
TEST
CONDITIONS
TIMING REQUIREMENTS
(1) TEHEL
(2) TELEH
(3) TELEL
External Frequency HIGH Time
External Frequency LOW Time
EFI Period
13 - ns 90%-90% VIN
13 - ns 10%-10% VIN
36 - ns
XTAL Frequency
2.4 25 MHz Note 2
(4) TR2VCL
RDY1, RDY2 Active Setup to CLK
35
- ns ASYNC = HIGH
(5) TR1VCH
RDY1, RDY2 Active Setup to CLK
35
- ns ASYNC = LOW
(6) TR1VCL
RDY1, RDY2 Inactive Setup to CLK
35
- ns
(7) TCLR1X
RDY1, RDY2 Hold to CLK
0 - ns
(8) TAYVCL
ASYNC Setup to CLK
50 - ns
(9) TCLAYX
ASYNC Hold to CLK
0 - ns
(10) TA1VR1V
AEN1, AEN2 Setup to RDY1, RDY2
15
- ns
(11) TCLA1X
AEN1, AEN2 Hold to CLK
0 - ns
(12) TYHEH
CSYNC Setup to EFI
20 - ns
(13) TEHYL
CSYNC Hold to EFI
20 - ns
(14) TYHYL
CSYNC Width
2 TELEL
- ns
(15) TI1HCL
(16) TCLI1H
TIMING RESPONSES
(17) TCLCL
(18) TCHCL
(19) TCLCH
(20) TCH1CH2
(21) TCL2CL1
RES Setup to CLK
RES Hold to CLK
CLK Cycle Period
CLK HIGH Time
CLK LOW Time
CLK Rise or Fall Time
65
20
125
(1/3 TCLCL) +2.0
(2/3 TCLCL) -15.0
-
-
-
-
-
-
10
ns Note 3
ns Note 3
ns Note 6
ns Note 6
ns Note 6
ns 1.0V to 3.0V
(22) TPHPL
PCLK HIGH Time
TCLCL-20
- ns Note 6
(23) TPLPH
PCLK LOW Time
TCLCL-20
- ns Note 6
(24) TRYLCL
Ready Inactive to CLK (See Note 4)
-8
- ns Note 4
(25) TRYHCH
Ready Active to CLK (See Note 3)
(2/3 TCLCL) -15.0
-
ns Note 5
(26) TCLIL
CLK to Reset Delay
- 40 ns
(27) TCLPH
CLK to PCLK HIGH Delay
- 22 ns
(28) TCLPL
CLK to PCLK LOW Delay
- 22 ns
(29) TOLCH
OSC to CLK HIGH Delay
-5 22 ns
(30) TOLCL
OSC to CLK LOW Delay
2 35 ns
NOTES:
1. Tested as follows: f = 2.4MHz, VIH = 2.6V, VIL = 0.4V, CL = 50pF, VOH 1.5V, VOL 1.5V, unless otherwise specified. RES and F/C must
switch between 0.4V and VCC -0.4V. Input rise and fall times driven at 1ns/V. VIL VIL (max) - 0.4V for CSYNC pin. VCC = 4.5V and 5.5V.
2. Tested using EFI or X1 input pin.
3. Setup and hold necessary only to guarantee recognition at next clock.
4. Applies only to T2 states.
5. Applies only to T3 TW states.
6. Tested with EFI input frequency = 4.2MHz.
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