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84067012A Schematic ( Datenblatt PDF ) - Intersil Corporation

Teilenummer 84067012A
Beschreibung CMOS Octal Latching Bus Driver
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 

Gesamt 7 Seiten
		
84067012A Datasheet, Funktion
82C82
March 1997
CMOS Octal Latching Bus Driver
Features
Description
• Full Eight-Bit Parallel Latching Buffer
• Bipolar 8282 Compatible
• Three-State Noninverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
• Gated Inputs:
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA
• Operating Temperature Ranges
- C82C82 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 82C82 is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon
gate CMOS process (Scaled SAJI IV). The 82C82 provides
an eight-bit parallel latch/buffer in a 20 pin package. The
active high strobe (STB) input allows transparent transfer of
data and latches data on the negative transition of this sig-
nal. The active low output enable (OE) permits simple inter-
face to state-of-the-art microprocessor systems.
Ordering Information
PART NUMBER
CP82C82
IP82C82
CS82C82
IS82C82
CD82C82
ID82C82
MD82C82/B
TEMP. RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
PACKAGE
20 Ld PDIP
20 Ld PLCC
20 Ld CERDIP
PKG. NO.
E20.3
N20.35
F20.3
8406701RA
MR82C82/B
SMD #
-55oC to +125oC 20 Pad CLCC J20.A
84067012A
SMD #
Pinouts
82C82 (PDIP, CERDIP)
TOP VIEW
82C82 (PLCC, CLCC)
TOP VIEW
DI0 1
DI1 2
DI2 3
DI3 4
DI4 5
DI5 6
DI6 7
DI7 8
OE 9
GND 10
20 VCC
19 DO0
18 DO1
17 DO2
16 DO3
15 DO4
14 DO5
13 DO6
12 DO7
11 STB
3 2 1 20 19
DI3 4
DI4 5
DI5 6
DI6 7
DI7 8
18 DO1
17 DO2
16 DO3
15 DO4
14 DO5
9 10 11 12 13
TRUTH TABLE
STB OE DI
DO
X H X Hi-Z
H LL L
H LH H
LX
H = Logic One
L = Logic Zero
X = Don’t Care
= Latched to Value of Last
Data
Hi-Z = High Impedance
= Neg. Transition
PIN NAMES
PIN
DI0-DI7
DO0-DO7
STB
OE
DESCRIPTION
Data Input Pins
Data Output Pins
Active High Strobe
Active Low Output
Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-274
File Number 2975.1






84067012A Datasheet, Funktion
Burn-In Circuits
82C82
R1
F2
R1
F2
R1
F2
R1
F2
R1
F2
R1
F2
R1
F2
R1
F2
R1
F0
MD82C82 CERDIP
VCC
C1
1 20
2 19 A
3 18 A
4 17 A
5 16 A
6 15 A
7 14 A
8 13 A A
9
12 R1
A
10 11 F1
VCC
R2
R2
F2 R3
F2 R3
F2 R3
F2 R3
F2 R3
NOTES:
1. VCC = 5.5 ± 0.5V, GND = 0V.
2. VIH = 4.5V ±10%.
3. VIL = -0.2V to 0.4V.
4. R1 = 47kΩ ±5%.
5. R2 = 2.0kΩ ±5%.
6. R3 = 4.2kΩ ±5%.
7. R4 = 470kΩ ±5%.
8. C1 = 0.01µF minimum.
9. F0 = 100kHz ±10%.
10. F1 = F0/2, F2 = F1/2.
MR82C82 CLCC
VCC
C1
F2 F2 F2
R3 R3 R3
VCC/2
R3
3 2 1 20 19
4 18 R3
5 17 R3
6 16 R3
7 15 R3
R3
8 14
9 10 11 12 13
R3 R3 R3 R3
F0 F1 VCC/2 VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
4-279

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