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8405202XA Schematic ( Datenblatt PDF ) - Intersil Corporation

Teilenummer 8405202XA
Beschreibung CMOS 16-Bit Microprocessor
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 

Gesamt 30 Seiten
		
8405202XA Datasheet, Funktion
80C86
March 1997
CMOS 16-Bit Microprocessor
[ /Title
(80C86
)
/Sub-
ject
(CMO
S 16-
Bit
Micro-
proces-
sor)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
Inter-
sil
Corpo-
ration,
16 Bit
uP,
micro-
proces-
sor,
8086,
PC)
/Cre-
Features
Description
• Compatible with NMOS 8086
• Completely Static CMOS Design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C86)
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2)
• Low Power Operation
- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500µA Max
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Typ
• 1MByte of Direct Memory Addressing Capability
• 24 Operand Addressing Modes
• Bit, Byte, Word and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
- Binary, or Decimal
- Multiply and Divide
• Wide Operating Temperature Range
- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
- l80C86 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M80C86 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 80C86 high performance 16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS pro-
cess (Scaled SAJI IV). Two modes of operation, minimum for
small systems and maximum for larger applications such as
multiprocessing, allow user configuration to achieve the
highest performance level. Full TTL compatibility (with the
exception of CLOCK) and industry standard operation allow
use of existing NMOS 8086 hardware and software designs.
Ordering Information
PACKAGE
PDIP
PLCC
CERDIP
SMD#
CLCC
SMD#
TEMP. RANGE 5MHz
8MHz
PKG.
NO.
0oC to +70oC CP80C86 CP80C86-2 E40.6
-40oC to +85oC lP80C86 IP80C86-2 E40.6
0oC to +70oC CS80C86 CS80C86-2 N44.65
-40oC to +85oC lS80C86 IS80C86-2 N44.65
0oC to +70oC CD80C86 CD80C86-2 F40.6
-40oC to +85oC ID80C86 ID80C86-2 F40.6
-55oC to +125oC MD80C86/B MD80C86- F40.6
2/B
-55oC to +125oC 8405201QA 8405202QA F40.6
-55oC to +125oC MR80C86/B MR80C86- J44.A
2/B
-55oC to +125oC 8405201XA 8405202XA J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
3-141
File Number 2957.1






8405202XA Datasheet, Funktion
80C86
Minimum Mode System (Continued)
The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to
minimum mode are described; all other pin functions are as described below.
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
DT/R
27
O DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data bus
transceiver. It is used to control the direction of data flow through the transceiver. Logically,
DT/R is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HIGH,
R = LOW). DT/R is held to a high impedance logic one during local bus “hold acknowledge”.
DEN
26
O DATA ENABLE: provided as an output enable for a bus transceiver in a minimum system which
uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA cy-
cles. For a read or INTA cycle it is active from the middle of T2 until the middle of T4, while for a
write cycle it is active from the beginning of T2 until the middle of T4. DEN is held to a high im-
pedance logic one during local bus “hold acknowledge”.
HOLD
HLDA
31, 30
I HOLD: indicates that another master is requesting a local bus “hold”. To be an acknowledged,
O HOLD must be active HIGH. The processor receiving the “hold” will issue a “hold acknowledge”
(HLDA) in the middle of a T4 or TI clock cycle. Simultaneously with the issuance of HLDA, the
processor will float the local bus and control lines. After HOLD is detected as being LOW, the
processor will lower HLDA, and when the processor needs to run another cycle, it will again drive
the local bus and control lines.
HOLD is not an asynchronous input. External synchronization should be provided if the system
cannot otherwise guarantee the setup time.
Maximum Mode System
The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are
unique to maximum mode are described below.
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
S0 26 O STATUS: is active during T4, T1 and T2 and is returned to the passive state (1, 1, 1) during T3
S1 27 O or during TW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate
S2 28 O all memory and I/O access control signals. Any change by S2, S1 or S0 during T4 is used to
indicate the beginning of a bus cycle, and the return to the passive state in T3 or TW is used to
indicate the end of a bus cycle.
These signals are held at a high impedance logic one state during “grant sequence”.
S2 S1 S0
CHARACTERISTICS
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive
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8405202XA pdf, datenblatt
80C86
External Interface
Processor RESET and Initialization
Processor initialization or start up is accomplished with activa-
tion (HIGH) of the RESET pin. The 80C86 RESET is required to
be HIGH for greater than 4 CLK cycles. The 80C86 will termi-
nate operations on the high-going edge of RESET and will
remain dormant as long as RESET is HIGH. The low-going
transition of RESET triggers an internal reset sequence for
approximately 7 clock cycles. After this interval, the 80C86
operates normally beginning with the instruction in absolute
location FFFF0H. (See Figure 2). The RESET input is internally
synchronized to the processor clock. At initialization, the HIGH-
to-LOW transition of RESET must occur no sooner than 50µs
(or 4 CLK cycles, whichever is greater) after power-up, to allow
complete initialization of the 80C86.
NMl will not be recognized prior to the second CLK cycle follow-
ing the end of RESET. If NMl is asserted sooner than nine clock
cycles after the end of RESET, the processor may execute one
instruction before responding to the interrupt.
Bus Hold Circuitry
To avoid high current conditions caused by floating inputs to
CMOS devices and to eliminate need for pull-up/down resistors,
“bus-hold” circuitry has been used on the 80C86 pins 2-16, 26-
32 and 34-39. (See Figure 4A and Figure 4B). These circuits
will maintain the last valid logic state if no driving source is
present (i.e., an unconnected pin or a driving source which
goes to a high impedance state). To overdrive the “bus hold” cir-
cuits, an external driver must be capable of supplying approxi-
mately 400µA minimum sink or source current at valid input
voltage levels. Since this “bus hold” circuitry is active and not a
“resistive” type element, the associated power supply current is
negligible and power dissipation is significantly reduced when
compared to the use of passive pull-up resistors.
OUTPUT
DRIVER
BOND
PAD
EXTERNAL
PIN
Interrupt Operations
Interrupt operations fall into two classes: software or hard-
ware initiated. The software initiated interrupts and software
aspects of hardware interrupts are specified in the Instruc-
tion Set Description. Hardware interrupts can be classified
as non-maskable or maskable.
Interrupts result in a transfer of control to a new program loca-
tion. A 256-element table containing address pointers to the
interrupt service program locations resides in absolute loca-
tions 0 through 3FFH, which are reserved for this purpose.
Each element in the table is 4 bytes in size and corresponds
to an interrupt “type”. An interrupting device supplies an 8-bit
type number during the interrupt acknowledge sequence,
which is used to “vector” through the appropriate element to
the new interrupt service program location. All flags and both
the Code Segment and Instruction Pointer register are saved
as part of the lNTA sequence. These are restored upon exe-
cution of an Interrupt Return (IRET) instruction.
Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable interrupt pin
(NMI) which has higher priority than the maskable interrupt
request pin (INTR). A typical use would be to activate a
power failure routine. The NMI is edge-triggered on a LOW-
to-HIGH transition. The activation of this pin causes a type 2
interrupt.
NMl is required to have a duration in the HIGH state of
greater than two CLK cycles, but is not required to be syn-
chronized to the clock. Any positive transition of NMI is
latched on-chip and will be serviced at the end of the current
instruction or between whole moves of a block-type instruc-
tion. Worst case response to NMI would be for multiply,
divide, and variable shift instructions. There is no specifica-
tion on the occurrence of the low-going edge; it may occur
before, during or after the servicing of NMI. Another positive
edge triggers another response if it occurs after the start of
the NMI procedure. The signal must be free of logical spikes
in general and be free of bounces on the low-going edge to
avoid triggering extraneous responses.
INPUT
BUFFER
INPUT
PROTECTION
CIRCUITRY
FIGURE 4A. BUS HOLD CIRCUITRY PIN 2-16, 34-39
OUTPUTVCC
DRIVER
P
BOND
PAD EXTERNAL
PIN
INPUT
BUFFER
INPUT
PROTECTION
CIRCUITRY
FIGURE 4B. BUS HOLD CIRCUITRY PIN 26-32
Maskable Interrupt (INTR)
The 80C86 provides a single interrupt request input (lNTR)
which can be masked internally by software with the reset-
ting of the interrupt enable flag (IF) status bit. The interrupt
request signal is level triggered. It is internally synchronized
during each clock cycle on the high-going edge of CLK. To
be responded to, lNTR must be present (HIGH) during the
clock period preceding the end of the current instruction or
the end of a whole move for a block type instruction. lNTR
may be removed anytime after the falling edge of the first
INTA signal. During the interrupt response sequence further
interrupts are disabled. The enable bit is reset as part of the
response to any interrupt (lNTR, NMI, software interrupt or
single-step), although the FLAGS register which is automati-
cally pushed onto the stack reflects the state of the proces-
sor prior to the interrupt. Until the old FLAGS register is
restored, the enable bit will be zero unless specifically set by
an instruction.
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