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83C752 Schematic ( Datenblatt PDF ) - NXP

Teilenummer 83C752
Beschreibung 80C51 8-bit microcontroller family 2K/64 OTP/ROM/ 5 channel 8 bit A/D/ I2C/ PWM/ low pin count
Hersteller NXP
Logo NXP Logo 

Gesamt 24 Seiten
		
83C752 Datasheet, Funktion
INTEGRATED CIRCUITS
83C752/87C752
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM,
low pin count
Product specification
Supersedes data of 1998 Jan 19
IC20 Data Handbook
1998 May 01
Philips
Semiconductors






83C752 Datasheet, Funktion
Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count
Product specification
83C752/87C752
OSCILLATOR CHARACTERISTICS
X1 and X2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator.
To drive the device from an external clock source, X1 should be
driven while X2 is left unconnected. There are no requirements on
the duty cycle of the external clock signal, because the input to the
internal clock circuitry is through a divide-by-two flip-flop. However,
minimum and maximum high and low times specified in the data
sheet must be observed.
IDLE MODE
The 8XC752 includes the 80C51 power-down and idle mode
features. In idle mode, the CPU puts itself to sleep while all of the
on-chip peripherals except the A/D and PWM stay active. The
functions that continue to run while in the idle mode are Timer 0, the
I2C interface including Timer I, and the interrupts. The instruction to
invoke the idle mode is the last instruction executed in the normal
operating mode before the idle mode is activated. The CPU
contents, the on-chip RAM, and all of the special function registers
remain intact during this mode. The idle mode can be terminated
either by any enabled interrupt (at which time the process is picked
up at the interrupt service routine and continued), or by a hardware
reset which starts the processor in the same manner as a power-on
reset. Upon powering-up the circuit, or exiting from idle mode,
sufficient time must be allowed for stabilization of the internal analog
reference voltages before an A/D conversion is started.
Special Function Registers
The special function registers (directly addressable only) contain all
of the 8XC751 registers except the program counter and the four
register banks. Most of the 21 special function registers are used to
control the on-chip peripheral hardware. Other registers include
arithmetic registers (ACC, B, PSW), stack pointer (SP) and data
pointer registers (DPH, DPL). Nine of the SFRs are bit addressable.
Data Pointer
The data pointer (DPTR) consists of a high byte (DPH) and a low
byte (DPL). In the 80C51 this register allows the access of external
data memory using the MOVX instruction. Since the 83C752 does
not support MOVX or external memory accesses, this register is
generally used as a 16-bit offset pointer of the accumulator in a
MOVC instruction. DPTR may also be manipulated as two
independent 8-bit registers.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the instruction
to invoke power-down is the last instruction executed. Only the
contents of the on-chip RAM are preserved. A hardware reset is the
only way to terminate the power-down mode. The control bits for the
reduced power modes are in the special function register PCON.
Table 1. External Pin Status During Idle and
Power-Down Modes
MODE
Port 0*
Port 1
Port 2
Idle
Power-down
Data
Data
* Except for PWM output (P0.4).
Data
Data
Data
Data
DIFFERENCES BETWEEN THE 8XC752 AND
THE 80C51
Program Memory
On the 8XC752, program memory is 2048 bytes long and is not
externally expandable, so the 80C51 instructions MOVX, LJMP, and
LCALL are not implemented. If these instructions are executed, the
appropriate number of instruction cycles will take place along with
external fetches; however, no operation will take place. The LJMP
may not respond to all program address bits. The only fixed
locations in program memory are the addresses at which execution
is taken up in response to reset and interrupts, which are as follows:
Program Memory
Event
Address
Reset
000
External INT0
003
Counter/timer 0
00B
External INT1
013
Timer I
I2C serial
01B
023
ADC
02B
PWM
033
Memory Organization
The 8XC752 manipulates operands in three memory address
spaces. The first is the program memory space which contains
program instructions as well as constants such as look-up tables.
The program memory space contains 2k bytes in the 8XC752.
The second memory space is the data memory array which has a
logical address space of 128 bytes. However, only the first 64 (0 to
3FH) are implemented in the 8XC752.
The third memory space is the special function register array having
a 128-byte address space (80H to FFH). Only selected locations in
this memory space are used (see Table 2). Note that the
architecture of these memory spaces (internal program memory,
internal data memory, and special function registers) is identical to
the 80C51, and the 8XC752 varies only in the amount of memory
physically implemented.
The 8XC752 does not directly address any external data or program
memory spaces. For this reason, the MOVX instructions in the
80C51 instruction set are not implemented in the 83C752, nor are
the alternate I/O pin functions RD and WR.
1998 May 01
6

6 Page







83C752 pdf, datenblatt
Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count
Product specification
83C752/87C752
COUNTER/TIMER
The 8XC752 counter/timer is designated Timer 0 and is separate
from Timer I of the I2C serial port and from the PWM. Its operation is
similar to mode 2 of the 80C51 counter/timer, extended to 16 bits.
When Timer 0 is used in the external counter mode, the T0 input
(P1.7) is sampled every S4P1. The counter/timer function is
controlled using the timer control register (TCON).
TCON Register
MSB
LSB
GATE
C/T
TF
TR
IE0 IT0 IE1
IT1
Position Symbol
Function
TCON.7 GATE 1 – Timer 0 is enabled only when INT0 pin is
high and TR is 1.
0 – Timer 0 is enabled only when TR is 1.
TCON.6 C/T 1 – Counter operation from T0 pin.
0 – Timer operation from internal clock.
TCON.5 TF 1 – Set on overflow of T0.
0 – Cleared when processor vectors to interrupt
routine and by reset.
TCON.4 TR 1 – Enable timer 0
0 – Disable timer 0
TCON.3 IE0 1 – Edge detected on INT0
TCON.2 IT0 1 – INT0 is edge triggered.
0 – INT0 is level sensitive.
TCON.1 IE1 1 – Edge detected on INT1
TCON.0 IT1 1 – INT1 is edge triggered.
0 – INT1 is level sensitive.
These flags are functionally identical to the corresponding 80C51
flags except that there is only one of the 80C51 style timers, and the
flags are combined into one register.
Note that the positions of the IE0/IT0 and IE1/IT1 bits are
transposed from the positions used in the standard 80C51 TCON
register.
A communications watchdog timer, Timer I, is described in the I2C
section. In I2C applications, this timer is dedicated to time generation
and bus monitoring for the I2C. In non-I2C applications, it is available
for use as a fixed time base.
The 16-bit timer/counter’s operation is similar to mode 2 operation
on the 80C51, but is extended to 16 bits. The timer/counter is
clocked by either 1/12 the oscillator frequency or by transitions on
the T0 pin. The C/T pin in special function register TCON selects
between these two modes. When the TCON TR bit is set, the
timer/counter is enabled. Register pair TH and TL are incremented
by the clock source. When the register pair overflows, the register
pair is reloaded with the values in registers RTH and RTL. The value
in the reload registers is left unchanged. The TF bit in special
function register TCON is set on counter overflow and, if the
interrupt is enabled, will generate an interrupt (see Figure 3).
OSC
T0 Pin
TR
÷ 12
C/T = 0
C/T = 1
TL TH
TF
Reload
Int.
Gate
INT0 Pin
RTL RTH
Figure 3. 83C752 Counter/Timer Block Diagram
Table 3. I2C Special Function Register Addresses
REGISTER ADDRESS
BIT ADDRESS
NAME
I2C control
I2C data
I2C configuration
I2C status
SYMBOL
I2CON
I2DAT
I2CFG
I2STA
ADDRESS MSB
98 9F 9E 9D 9C 9B
99 – – – – –
D8 DF DE DD DC DB
F8 FF FE FD FC FB
SU00300
LSB
9A
DA
FA
99
D9
F9
98
D8
F8
1998 May 01
12

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