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83C751 Schematic ( Datenblatt PDF ) - NXP

Teilenummer 83C751
Beschreibung 80C51 8-bit microcontroller family 2K/64 OTP/ROM/ I2C/ low pin count
Hersteller NXP
Logo NXP Logo 

Gesamt 24 Seiten
		
83C751 Datasheet, Funktion
INTEGRATED CIRCUITS
83C751/87C751
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
Product specification
Supersedes data of 1998 Jan 19
IC20 Data Handbook
1998 May 01
Philips
Semiconductors






83C751 Datasheet, Funktion
Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
Product specification
83C751/87C751
ABSOLUTE MAXIMUM RATINGS1, 2
PARAMETER
RATING
UNIT
Storage temperature range
–65 to +150
°C
Voltage from VCC to VSS
Voltage from any pin to VSS (except VPP)
Power dissipation
–0.5 to +6.5
–0.5 to VCC + 0.5
1.0
V
V
W
Voltage on VPP pin to VSS
0 to +13.0
V
Maximum IOL per I/O pin
10 mA
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10% for 87C751, VCC = 5V ±10% for 83C751, VSS = 0V1
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
MIN MAX
VIL
VIH
VIH1
VIL1
VIH2
VOL
VOL1
VOH
VOL2
C
Input low voltage, except SDA, SCL
Input high voltage, except X1, RST
Input high voltage, X1, RST
SDA, SCL, P0.2
Input low voltage
Input high voltage
Output low voltage, ports 1 and 3
Output low voltage, port 0.2
Output high voltage, ports 1 and 3
Port 0.0 and 0.1 (I2C) – Drivers
Output low voltage
Driver, receiver combined:
Capacitance
IOL = 1.6mA2
IOL = 3.2mA2
IOH = –60µA
IOH = –25µA
IOH = –10µA
IOL = 3mA
(over VCC range)
–0.5
0.2VCC+0.9
0.7VCC
0.2VDD–0.1
VCC+0.5
VCC+0.5
–0.5
0.7VCC
2.4
0.75VCC
0.9VCC
0.3VCC
VCC+0.5
0.45
0.45
0.4
10
IIL
ITL
ILI
RRST
CIO
IPD
VPP
Logical 0 input current, ports 1 and 3
Logical 1 to 0 transition current, ports 1 and 33
Input leakage current, port 0
Internal pull-down resistor
Pin capacitance
Power-down current4
VPP program voltage (for 87C751 only)
VIN = 0.45V
VIN = 2V (0 to 70°C)
VIN = 2V (–40 to +85°C)
0.45 < VIN < VCC
Test freq = 1MHz,
Tamb = 25°C
VCC = 2 to VCC max
VSS = 0V
VCC = 5V±10%
Tamb = 21°C to 27°C
25
12.5
–50
–650
–750
±10
175
10
50
13.0
IPP Program current (for 87C751 only)
ICC Supply current (see Figure 2)
NOTES TO DC ELECTRICAL CHARACTERISTICS ON NEXT PAGE.
VPP = 13.0V
50
UNIT
V
V
V
V
V
V
V
V
V
V
V
pF
µA
µA
µA
µA
k
pF
µA
V
mA
1998 May 01
6

6 Page







83C751 pdf, datenblatt
Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
Product specification
83C751/87C751
I/O Port Structure
The 8XC751 has two 8-bit ports (ports 1 and 3) and one 3-bit port
(port 0). All three ports on the 8XC751 are bidirectional. Each
consists of a latch (special function register P0, P1, P3), an output
driver, and an input buffer. Three port 1 pins and two port 0 pins are
multifunctional. In addition to being port pins, these pins serve the
function of special features as follows:
Port PinAlternate Function
P0.0 I2C clock (SCL)
P0.1 I2C data (SDA)
P1.5 INT0 (external interrupt 0 input)
P1.6 INT1 (external interrupt 1 input)
P1.7 T0 (timer 0 external input)
Ports 1 and 3 are identical in structure to the same ports on the
80C51. The structure of port 0 on the 8XC751 is similar to that of the
80C51 but does not include address/data input and output circuitry.
As on the 80C51, ports 1 and 3 are quasi-bidirectional while port 0 is
bidirectional with no internal pullups.
Timer/Counter
The 8XC751 has two timers: a 16-bit timer/counter and a 10-bit
fixed-rate timer. The 16-bit timer/counter’s operation is similar to
mode 2 operation on the 80C51, but is extended to 16 bits. The
timer/counter is clocked by either 1/12 the oscillator frequency or by
transitions on the T0 pin. The C/T pin in special function register
TCON selects between these two modes. When the TCON TR bit is
set, the timer/counter is enabled. Register pair TH and TL are
incremented by the clock source. When the register pair overflows,
the register pair is reloaded with the values in registers RTH and
RTL. The value in the reload registers is left unchanged. See the
83C751 counter/timer block diagram in Figure 4. The TF bit in
special function register TCON is set on counter overflow and, if the
interrupt is enabled, will generate an interrupt.
TCON Register
MSB
LSB
GATE C/T TF TR IE0 IT0 IE1 IT1
GATE 1
0
C/T 1
0
TF 1
0
TR 1
0
IE0 1
IT0 1
0
IE1 1
IT1 1
0
– Timer/counter is enabled only when INT0 pin is
high, and TR is 1.
– Timer/counter is enabled when TR is 1.
– Counter/timer operation from T0 pin.
– Timer operation from internal clock.
– Set on overflow of TH.
– Cleared when processor vectors to interrupt routine
and by reset.
– Timer/counter enabled.
– Timer/counter disabled.
– Edge detected in INT0.
– INT0 is edge triggered.
– INT0 is level sensitive.
– Edge detected on INT1.
– INT1 is edge triggered.
– INT1 is level sensitive.
These flags are functionally identical to the corresponding 80C51
flags, except that there is only one timer on the 83C751 and the
flags are therefore combined into one register.
Note that the positions of the IE0/IT0 and IE1/IT1 bits are
transposed from the positions used in the standard 80C51 TCON
register.
Timer I is used to control the timing of the I2C bus and also to detect
a “bus locked” condition, by causing an interrupt when nothing
happens on the I2C bus for an inordinately long period of time while
a transmission is in progress. If the interrupt does not occur, the
program can attempt to correct the fault and allow the last I2C
transmission to be repeated.
The I2C watchdog timer, timer I, is also available as a
general-purpose fixed-rate timer when the I2C interface is not being
used. A clock rate of 1/12 the oscillator frequency forms the input to
the timer. Timer I has a timeout interval of 1024 machine cycles
when used as a fixed-rate timer.
OSC
T0 Pin
TR
Gate
INT0 Pin
÷ 12
C/T = 0
C/T = 1
TL TH
Reload
RTL RTH
Figure 4. 83C751 Counter/Timer Block Diagram
TF
Int.
SU00300
1998 May 01
12

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