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83C748 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer 83C748
Beschreibung 80C51 8-bit microcontroller family 2K/64 OTP/ROM/ low pin count
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 18 Seiten
83C748 Datasheet, Funktion
INTEGRATED CIRCUITS
83C748/87C748
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
Preliminary specification
Supersedes data of 1998 Apr 23
IC20 Data Handbook
1999 Apr 15
Philips
Semiconductors






83C748 Datasheet, Funktion
Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
Preliminary specification
83C748/87C748
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V1, 2
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/tCLCL
Oscillator frequency:
3.5 12 MHz
3.5 16 MHz
External Clock (Figure 1)
tCHCX
High time
20 20 ns
tCLCX
Low time
20 20 ns
tCLCH
Rise time
20 20 ns
tCHCL
Fall time
20 20 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.
2. Load capacitance for ports = 80pF.
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
C – Clock
D – Input data
H – Logic level high
L – Logic level low
Q – Output data
T – Time
V – Valid
X – No longer a valid logic level
Z – Float
VCC –0.5
0.45V
0.2 VCC + 0.9
0.2 VCC – 0.1
tCLCX
tCHCL
tCLCL
tCHCX
tCLCH
Figure 1. External Clock Drive
SU00297
ROM CODE SUBMISSION
When submitting ROM code for the 83C748, the following must be specified:
1. 2k byte user ROM data
ADDRESS
0000H to 07FFH
CONTENT
DATA
BIT(S)
7:0
COMMENT
User ROM Data
1999 Apr 15
6

6 Page









83C748 pdf, datenblatt
Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
Preliminary specification
83C748/87C748
Security Bits
Two security bits, security bit 1 and security bit 2, are provided to
limit access to the USER EPROM and encryption key arrays.
Security bit 1 is the program inhibit bit, and once programmed
performs the following functions:
1. Additional programming of the USER EPROM is inhibited.
2. Additional programming of the encryption key is inhibited.
3. Verification of the encryption key is inhibited.
4. Verification of the USER EPROM and the security bit levels may
still be performed.
(If the encryption key array is being used, this security bit should be
programmed by the user to prevent unauthorized parties from
reprogramming the encryption key to all logical zero bits. Such
programming would provide data during a verify cycle that is the
logical complement of the USER EPROM contents).
Security bit 2, the verify inhibit bit, prevents verification of both the
USER EPROM array and the encryption key arrays. The security bit
levels may still be verified.
Programming and Verifying Security Bits
Security bits are programmed employing the same techniques used
to program the USER EPROM and KEY arrays using serial data
streams and logic levels on port pins indicated in Table 3. When
programming either security bit, it is not necessary to provide
address or data information to the 87C748 on ports 1 and 3.
Verification occurs in a similar manner using the RESET serial
stream shown in Table 3. Port 3 is not required to be driven and the
results of the verify operation will appear on ports 1.6 and 1.7.
Ports 1.7 contains the security bit 1 data and is a logical one if
programmed and a logical zero if not programmed. Likewise, P1.6
contains the security bit 2 data and is a logical one if programmed
and a logical zero if not programmed.
EPROM PROGRAMMING AND VERIFICATION
Tamb = 21°C to +27°C, VCC = 5V ±10%, VSS = 0V
SYMBOL
PARAMETER
MIN
1/tCLCL
Oscillator/clock frequency
1.2
tAVGL1
Address setup to P0.1 (PROG–) low
10µs + 24tCLCL
tGHAX
Address hold after P0.1 (PROG–) high
48tCLCL
tDVGL
Data setup to P0.1 (PROG–) low
38tCLCL
tGHDX
Data hold after P0.1 (PROG–) high
36tCLCL
tSHGL
VPP setup to P0.1 (PROG–) low
10
tGHSL
VPP hold after P0.1 (PROG–)
10
tGLGH
P0.1 (PROG–) width
90
tAVQV2
VPP low (VCC) to data valid
tGHGL
P0.1 (PROG–) high to P0.1 (PROG–) low
10
tMASEL
ASEL high time
13tCLCL
tHAHLD
Address hold time
2tCLCL
tHASET
Address setup to ASEL
13tCLCL
tADSTA
Low address to valid data
NOTES:
1. Address should be valid at least 24tCLCL before the rising edge of P0.2 (VPP).
2. For a pure verify mode, i.e., no program mode in between, tAVQV is 14tCLCL maximum.
MAX
6
110
48tCLCL
48tCLCL
UNIT
MHz
µs
µs
µs
µs
1999 Apr 15
12

12 Page





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