Datenblatt-pdf.com

83C575 Schematic ( Datenblatt PDF ) - NXP

Teilenummer 83C575
Beschreibung 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless/ 4 comparator/ failure detect circuitry/ watchdog timer
Hersteller NXP
Logo NXP Logo 

Gesamt 30 Seiten
		
83C575 Datasheet, Funktion
INTEGRATED CIRCUITS
80C575/83C575/87C575
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator,
failure detect circuitry, watchdog timer
Product specification
Supersedes data of 1998 Jan 27
IC20 Data Handbook
1998 May 01
Philips
Semiconductors






83C575 Datasheet, Funktion
Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
Product specification
80C575/83C575/
87C575
PIN DESCRIPTIONS (Continued)
PIN NUMBER
MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION
Port 3: (continued)
10 11
5
I P3.0 RxD Serial receive port
11 13
7
O P3.1 TxD
Serial transmit port enabled only when transmitting serial data
12 14
8
I P3.2 INT0 External interrupt 0
13 15
9
I P3.3 INT1 External interrupt 1
14 16 10
I P3.4 T0
Timer/counter 0 input
CMPR- Common - reference to comparators 1, 2, 3
15 17 11
I P3.5 T1
Timer/counter 1 input
CMP1+ Comparator 1 positive input
16 18 12 O P3.6 WR External data memory write strobe
CMP2+ Comparator 2 positive input
17 19 13
O P3.7 RD
External data memory read strobe
CMP3+ Comparator 3 positive input
RST
9 10 4
I Reset: A low on this pin asynchronously resets all port pins to a low state except P3.1. The
pin must be held low with the oscillator running for 24 oscillator cycles to initialize the
internal registers. An internal diffused resistor to VCC permits a power on reset using only
an external capacitor to VSS. RST has a Schmitt trigger input stage to provide additional
noise immunity with a slow rising input voltage.
ALE/PROG 30 33 27 I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.
Note that one ALE pulse is skipped during each access to external data memory. ALE is
switched off if the bit 0 in the AUXR register (8EH) is set. This pin is also the program pulse
input (PROG) during EPROM programming.
PSEN
29 32 26 O Program Store Enable: The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.
EA/VPP
XTAL1
31 35 29
19 21 15
I External Access Enable/Programming Supply Voltage: EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H to
1FFFH. If EA is held high, the device executes from internal program memory unless the
program counter contains an address greater than 1FFFH. This pin also receives the
12.75V programming supply voltage (VPP) during EPROM programming.
I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2
18 20 14 O Crystal 2: Output from the inverting oscillator amplifier.
1998 May 01
6

6 Page







83C575 pdf, datenblatt
Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
Product specification
80C575/83C575/
87C575
CMOD Address = OD9H
Reset Value = 00XX X000B
CIDL WDTE
CPS1
CPS0 ECF
Bit: 7 6 5 4 3 2 1 0
Symbol Function
CIDL
WDTE
CPS1
CPS0
ECF
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.
Not implemented, reserved for future use.*
PCA Count Pulse Select bit 1.
PCA Count Pulse Select bit 0.
CPS1 CPS0 Selected PCA Input**
00
01
10
0 Internal clock, fOSC ÷ 12
1 Internal clock, fOSC ÷ 4
2 Timer 0 overflow
11
3 External clock at ECI/P1.2 pin (max. rate = fOSC ÷ 8)
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
** fOSC = oscillator frequency
SU00035
Figure 5. CMOD: PCA Counter Mode Register
CCON Address = OD8H
Reset Value = 00X0 0000B
Symbol
CF
CR
CCF4
CCF3
CCF2
CCF1
CCF0
Bit Addressable
CF
Bit: 7
CR
6
– CCF4 CCF3 CCF2 CCF1 CCF0
543210
Function
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
Not implemented, reserved for future use*.
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU00036
Figure 6. CCON: PCA Counter Control Register
1998 May 01
12

12 Page


SeitenGesamt 30 Seiten
PDF Download[ 83C575.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
83C57580C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless/ 4 comparator/ failure detect circuitry/ watchdog timerNXP
NXP
83C57680C51 8-bit microcontroller family 8K/256 OTP/ROM/ 6 channel 10-bit A/D/ 4 comparators/ failure detect circuitry/ watchdog timerNXP
NXP

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com    |   2018   |  Kontakt  |   Suche