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83C196LC Schematic ( Datenblatt PDF ) - Intel Corporation

Teilenummer 83C196LC
Beschreibung CHMOS 16-BIT MICROCONTROLLER
Hersteller Intel Corporation
Logo Intel Corporation Logo 

Gesamt 22 Seiten
		
83C196LC Datasheet, Funktion
ADVANCE INFORMATION
83C196LC, 83C196LD
CHMOS 16-BIT MICROCONTROLLER
Automotive
s 22 MHz operation
s 32 Kbytes of on-chip ROM (LC)
16 Kbytes of on-chip ROM (LD)
s 1 Kbyte of on-chip register RAM (LC)
384 bytes of on-chip register RAM (LD)
s 512 bytes of on-chip code RAM
(LC only)
s Register-to-register architecture
s Peripheral transaction server (PTS)
with high-speed, microcoded interrupt
service routines
s Full-duplex serial I/O port with
dedicated baud-rate generator
s Enhanced full-duplex, synchronous
serial I/O port (SSIO)
12 MHz standard; 18 MHz and 22 MHz are speed
premium
s High-speed event processor array
— Six capture/compare channels
— Two compare-only channels
— Two 16-bit software timers
s Programmable 8- or 16-bit external bus
s Design enhancements for EMI
reduction
s Oscillator failure detection circuitry
s SFR register that indicates the source
of the last reset
s Watchdog timer (WDT)
s Cost reduced replacements for the
87C196JT and 87C196JR.
s 40° C to +125° C ambient temperature
s 52-pin PLCC package
NOTE
This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify
with your local Intel sales office that you have the latest datasheet before finalizing a
design.
The 83C196LC, 83C196LD are low-cost, pin-compatible replacements for the existing 87C196JT and
87C196JR, respectively. These products feature an enhanced synchronous serial I/O (SSIO) port for more
flexible communication to other devices. The enhanced SSIO is compatible with Motorola’s Serial Peripheral
Interface (SPI) protocol and National’s Microwire protocol. To optimize die size, the A/D converter was
removed for use in those applications that use an off-chip A/D converter.
The MCS® 96 microcontroller family members are all high-performance microcontrollers with 16-bit CPUs.
The 83C196LC, 83C196LD are composed of a high-speed core with the following peripherals: an
asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud-rate generator; an
additional synchronous serial I/O port with full duplex master/slave transceivers; a flexible timer/counter
structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O
for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs;
and a sophisticated, prioritized interrupt structure with programmable peripheral transaction server (PTS).
The 83C196LC has the highest memory density of the 52-pin MCS 96 microcontroller family, with 32 Kbytes
of on-chip ROM, 1 Kbyte of on-chip register RAM, and 512 bytes of code RAM. The high memory integration
of the 83C196LC supports high functionality in a low pin-count package and the use of the C programming
language.
COPYRIGHT © INTEL CORPORATION, 1996
December 1996
Order Number: 272805-001






83C196LC Datasheet, Funktion
83C196LC, 83C196LD — AUTOMOTIVE
3.0 SIGNALS
Name
AD15:0
ADV#
ALE
CLKOUT
EA#
EPA9:8
EPA3:0
Type
I/O
O
O
O
I
I/O
Table 4. Signal Descriptions
Description
Address/Data Lines
These pins provide a multiplexed address and data bus. During the address
phase of the bus cycle, address bits 0–15 are presented on the bus and can be
latched using ALE or ADV#. During the data phase, 8- or 16-bit data is
transferred.
AD7:0 share package pins with P3.7:0. AD15:8 share package pins with P4.7:0.
Address Valid
This active-low output signal is asserted only during external memory
accesses. ADV# indicates that valid address information is available on the
system address/data bus. The signal remains low while a valid bus cycle is in
progress and is returned high as soon as the bus cycle completes.
An external latch can use this signal to demultiplex the address from the
address/data bus. A decoder can also use this signal to generate chip selects
for external memory.
ADV# shares a package pin with P5.0 and ALE.
Address Latch Enable
This active-high output signal is asserted only during external memory cycles.
ALE signals the start of an external bus cycle and indicates that valid address
information is available on the system address/data bus.
An external latch can use this signal to demultiplex the address from the
address/data bus.
Output
Output of the internal clock generator. The CLKOUT frequency is ½ the
oscillator input frequency (FXTAL1). CLKOUT has a 50% duty cycle.
CLKOUT shares a package pin with P2.7
External Access
This input determines whether memory accesses to special-purpose and
program memory partitions are directed to internal or external memory. These
accesses are directed to internal memory if EA# is held high and to
externalmemory if EA# is held low. For an access to any other memory location,
the value of EA# is irrelevant.
EA# is sampled and latched only on the rising edge of RESET#. Changing the
level of EA# after reset has no effect.
Event Processor Array (EPA) Capture/Compare Channels
High-speed input/output signals for the EPA capture/compare channels.
The EPA signals share package pins with the following signals:
EPA0/P1.0/T2CLK, EPA1/P1.1, EPA2/P1.2/T2DIR, EPA3/P1.3,
EPA8/P6.0/COMP0, and EPA9/P6.1/COMP1. EPA7 does not connect to a
package pin. It cannot be used to capture an event, but it can function as a
software timer. EPA6:4 are not implemented.
6 ADVANCE INFORMATION

6 Page







83C196LC pdf, datenblatt
83C196LC, 83C196LD — AUTOMOTIVE
5.1 DC Characteristics
Symbol
Table 6. DC Characteristics at VCC = 4.5V – 5.5V
Parameter
Min Typical Max Units
Test Conditions
ICC VCC supply current
(40° C to +125° C
ambient)
ICC1 Active mode supply cur-
rent (typical)
FXTAL1 = 20 MHZ,
88 mA VCC = VPP = 5.5V
(While device is in reset)
55 mA
IIDLE Idle mode current
IPD Powerdown mode
current
20 40 mA FXTAL1 = 20 MHz,
VCC = VPP = 5.5V
50
TBD
µA
VCC = VPP = 5.5V
(Note 6)
VIL Input low voltage
(all pins)
–0.5V
0.3 VCC
V
VIH
Input high voltage (all
0.7 VCC
pins)
VCC + 0.5 V
VOL Output low voltage
(outputs configured as
complementary)
VOH Output high voltage VCC – 0.3
(outputs configured as VCC – 0.7
complementary)
VCC – 1.5
0.3
0.45
1.5
V IOL = 200 µA (Notes 3, 5)
V IOL = 3.2 mA
V IOL = 7.0 mA
V IOH = –200 µA (Notes 3, 5)
V IOH = –3.2 mA
V IOH = –7.0 mA
ILI Input leakage current
(standard inputs, ports
3 & 4)
± 10
µA VSS VIN VCC (Note 2)
ILI1 Input leakage current
(port 0)
± 2.0
µA VSS VIN VREF
IIH Input high current (NMI
pin)
+175
µA VSS VIN VCC
VOH2
Output high voltage in
reset
VCC – 1V
V IOH = –15 µA (Note 1)
IOH2 Output high current in
reset
–25
–45
–50
–120
–240
–280
µA VOH2 = VCC – 1.0V
µA VOH2 = VCC – 2.5V
µA VOH2 = VCC – 4.0V
RRST
Reset pullup resistor
6K
65K
NOTES:
1. All bidirectional pins except CLKOUT. CLKOUT is not pulled weakly high in reset. Bidirectional pins
include ports 1–6.
2. Standard input pins include XTAL1, EA#, RESET#, P0.7:2, and ports 1–6 when configured as inputs.
3. All bidirectional pins when configured as complementary outputs.
4. Device is static and should operate below 1 Hz, but is only tested down to 4 MHz.
5. Maximum IOLor IOH currents per pin will be characterized and published at a later date. Target values
are ± 10 mA.
6. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at
room temperature and VCC = 5.0V.
12 ADVANCE INFORMATION

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