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82C59A Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer 82C59A
Beschreibung CMOS Priority Interrupt Controller
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 20 Seiten
82C59A Datasheet, Funktion
82C59A
March 1997
CMOS Priority Interrupt Controller
Features
Description
• 12.5MHz, 8MHz and 5MHz Versions Available
- 12.5MHz Operation . . . . . . . . . . . . . . . . . . . 82C59A-12
- 8MHz Operation . . . . . . . . . . . . . . . . . . . . . . . 82C59A
- 5MHz Operation . . . . . . . . . . . . . . . . . . . . . . 82C59A-5
• High Speed, “No Wait-State” Operation with 12.5MHz
80C286 and 8MHz 80C86/88
• Pin Compatible with NMOS 8259A
• 80C86/88/286 and 8080/85/86/88/286 Compatible
• Eight-Level Priority Controller, Expandable to
64 Levels
• Programmable Interrupt Modes
• Individual Request Mask Capability
• Fully Static Design
• Fully TTL Compatible
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . 10µA Maximum
- ICCOP . . . . . . . . . . . . . . . . . . . . . 1mA/MHz Maximum
The Intersil 82C59A is a high performance CMOS Priority
Interrupt Controller manufactured using an advanced 2µm
CMOS process. The 82C59A is designed to relieve the sys-
tem CPU from the task of polling in a multilevel
priority system. The high speed and industry standard
configuration of the 82C59A make it compatible with micro-
processors such as 80C286, 80286, 80C86/88, 8086/88,
8080/85 and NSC800.
The 82C59A can handle up to eight vectored priority inter-
rupting sources and is cascadable to 64 without additional
circuitry. Individual interrupting sources can be masked or
prioritized to allow custom system configuration. Two modes
of operation make the 82C59A compatible with both 8080/85
and 80C86/88/286 formats.
Static CMOS circuit design ensures low operating power.
The Intersil advanced CMOS process results in performance
equal to or greater than existing equivalent products at a
fraction of the power.
• Single 5V Power Supply
• Operating Temperature Ranges
- C82C59A . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C59A . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C59A . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Ordering Information
5MHz
CP82C59A-5
IP82C59A-5
CS82C59A-5
IS82C59A-5
CD82C59A-5
ID82C59A-5
MD82C59A-5/B
5962-8501601YA
MR82C59A-5/B
5962-85016013A
CM82C59A-5
PART NUMBER
8MHz
CP82C59A
IP82C59A
CS82C59A
IS82C59A
CD82C59A
ID82C59A
MD82C59A/B
5962-8501602YA
MR82C59A/B
5962-85016023A
CM82C59A
12.5MHz
CP82C59A-12
IP82C59A-12
CS82C59A-12
IS82C59A-12
CD82C59A-12
ID82C59A-12
MD82C59A-12/B
-
MR82C59A-12/B
-
CM82C59A-12
PACKAGE
28 Ld PDIP
28 Ld PLCC
CERDIP
SMD#
28 Pad CLCC
SMD#
28 Ld SOIC
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
0oC to +70oC
PKG. NO.
E28.6
E28.6
N28.45
N28.45
F28.6
F28.6
F28.6
F28.6
J28.A
J28.A
M28.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-1
File Number 2784.2






82C59A Datasheet, Funktion
82C59A
ADDRESS BUS (16)
CONTROL BUS
DATA BUS (8)
I/OR I/OW INT INTA
CASCADE
LINES
CS
CAS 0
CAS 1
CAS 2
SP/EN
A0
D7 - D0
RD WR
82C59A
IRQ IRQ IRQ IRQ IRQ IRQ
7 6 543 2
INT INTA
IRQ IRQ
10
SLAVE PROGRAM/
ENABLE BUFFER
INTERRUPT
REQUESTS
FIGURE 5. 82C59A STANDARD SYSTEM BUS INTERFACE
6. This completes the interrupt cycle. In the AEOI mode, the
ISR bit is reset at the end of the second INTA pulse. Oth-
erwise, the ISR bit remains set until an appropriate EOI
command is issued at the end of the interrupt subroutine.
If no interrupt request is present at step 4 of either sequence
(i.e., the request was too short in duration), the 82C59A will
issue an interrupt level 7. If a slave is programmed on IR bit
7, the CAS lines remain inactive and vector addresses are
output from the master 82C59A.
Interrupt Sequence Outputs
8080, 8085 Interrupt Response Mode
This sequence is timed by three INTA pulses. During the first
lNTA pulse, the CALL opcode is enabled onto the data bus.
First Interrupt Vector Byte Data: Hex CD
D7 D6 D5 D4 D3 D2 D1 D0
Call Code 1 1 0 0 1 1 0 1
During the second INTA pulse, the lower address of the
appropriate service routine is enabled onto the data bus.
When interval = 4 bits, A5 - A7 are programmed, while
A0 - A4 are automatically inserted by the 82C59A. When
interval = 8, only A6 and A7 are programmed, while A0 - A5
are automatically inserted.
CONTENT OF SECOND INTERRUPT VECTOR BYTE
IR INTERVAL = 4
D7 D6 D5 D4 D3 D2 D1 D0
7 A7 A6 A5 1 1 1 0 0
6 A7 A6 A5 1 1 0 0 0
5 A7 A6 A5 1 0 1 0 0
4 A7 A6 A5 1 0 0 0 0
3 A7 A6 A5 0 1 1 0 0
2 A7 A6 A5 0 1 0 0 0
1 A7 A6 A5 0 0 1 0 0
0 A7 A6 A5 0 0 0 0 0
IR INTERVAL = 8
D7 D6 DS D4 D3 D2 D1 D0
7 A7 A6 1 1 1 0 0 0
6 A7 A6 1 1 0 0 0 0
5 A7 A6 1 0 1 0 0 0
4 A7 A6 1 0 0 0 0 0
3 A7 A6 0 1 1 0 0 0
2 A7 A6 0 1 0 0 0 0
1 A7 A6 0 0 1 0 0 0
0 A7 A6 0 0 0 0 0 0
During the third INTA pulse, the higher address of the appro-
priate service routine, which was programmed as byte 2 of the
initialization sequence (A8 - A15), is enabled onto the bus.
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82C59A pdf, datenblatt
82C59A
The Special Mask Mode is set by OCW3 where: ESMM = 1,
SMM = 1, and cleared where ESMM = 1, SMM = 0.
Poll Command
In this mode, the INT output is not used or the microproces-
sor internal Interrupt Enable flip flop is reset, disabling its
interrupt input. Service to devices is achieved by software
using a Poll command.
The Poll command is issued by setting P = 1 in OCW3. The
82C59A treats the next RD pulse to the 82C59A (i.e., RD =
0, CS = 0) as an interrupt acknowledge, sets the appropriate
IS bit if there is a request, and reads the priority level. Inter-
rupt is frozen from WR to RD.
The word enabled onto the data bus during RD is:
D7 D6 D5 D4 D3 D2 D1 D0
I - - - - W2 W1 W0
W0 - W2: Binary code of the highest priority level request-
ing service.
I: Equal to a “1” if there is an interrupt.
This mode is useful if there is a routine command common to
several levels so that the INTA sequence is not needed (saves
ROM space). Another application is to use the poll mode to
expand the number of priority levels to more than 64.
LTIM BIT
0 = EDGE
1 = LEVEL
EDGE
SENSE
LATCH
TO OTHER PRIORITY CELLS
VCC
CLR
Q
SET
IR
8080/85
MODE
INTA
FREEZE
REQUEST
LATCH
DQ
CQ
MASK LATCH
DQ
C
CLR
80C86/
88/286
MODE
INTA
FREEZE
FREEZE
READ WRITE
IRR MASK
CLR
Q
SET
IN - SERVICE
LATCH
CLR ISR
ISR BIT
SET ISR
PRIORITY
RESOLVER
NON-
MASKED
REQ
CONTROL
LOGIC
READ IMR
READ ISR
MASTER CLEAR
NOTES:
1. Master clear active only during ICW1.
2. FREEZE is active during INTA and poll sequence only.
3. Truth Table for D-latch.
C D Q Operation
1 D1 D1 Follow
0
X
Qn-1
Hold
FIGURE 9. PRIORITY CELL - SIMPLIFIED LOGIC DIAGRAM
Reading the 82C59A Status
The input status of several internal registers can be read to
update the user information on the system. The following
registers can be read via OCW3 (lRR and ISR) or OCW1
(lMR).
Interrupt Request Register (IRR): 8-bit register which con-
tains the levels requesting an interrupt to be acknowledged.
The highest request level is reset from the lRR when an
interrupt is acknowledged. lRR is not affected by lMR.
In-Service Register (ISR): 8-bit register which contains the
priority levels that are being serviced. The ISR is updated
when an End of Interrupt Command is issued.
Interrupt Mask Register: 8-bit register which contains the
interrupt request lines which are masked.
The lRR can be read when, prior to the RD pulse, a Read
Register Command is issued with OCW3 (RR = 1, RIS = 0).
The ISR can be read when, prior to the RD pulse, a Read
Register Command is issued with OCW3 (RR = 1, RIS = 1).
There is no need to write an OCW3 before every status read
operation, as long as the status read corresponds with the
previous one: i.e., the 82C59A “remembers” whether the lRR
or ISR has been previously selected by the OCW3. This is
not true when poll is used. In the poll mode, the 82C59A
4-12

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