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82C55A Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer 82C55A
Beschreibung CMOS Programmable Peripheral Interface
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 30 Seiten
82C55A Datasheet, Funktion
Data Sheet
December 8, 2015
82C55A
FN2969.11
CMOS Programmable Peripheral Interface
The Intersil 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may
be used with many different microprocessors. There are 24
I/O pins which may be individually programmed in 2 groups
of 12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.
Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
(See Ordering Info)
• Pin Compatible with NMOS 8255A
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 5MHz and
8MHz 80C86 and 80C88
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . . . .10A
Ordering Information
PART NUMBERS
5MHz
PART
MARKING
8MHz
PART
MARKING
CP82C55A-5
(No longer available,
recommended
replacement:
CP82C55A-5Z)
CP82C55A-5
CP82C55A
CP82C55A
CP82C55A-5Z (Note) CP82C55A-5Z CP82C55AZ (Note) CP82C55AZ
IP82C55A
IP82C55A
IP82C55AZ (Note) IP82C55AZ
CS82C55A-5*
(No longer available,
recommended
replacement:
CS82C55A-5Z)
CS82C55A-5
CS82C55A*
CS82C55A*
CS82C55A-5Z* (Note) CS82C55A-5Z CS82C55AZ* (Note) CS82C55AZ
IS82C55A-5*
IS82C55A-5 IS82C55A*
IS82C55A*
IS82C55A-5Z* (Note) IS82C55A-5Z IS82C55AZ* (Note) IS82C55AZ
CQ82C55AZ (Note) CQ82C55AZ
IQ82C55AZ* (Note) IQ82C55AZ
ID82C55A
ID82C55A
MD82C55A/B
MD82C55A/B
8406602QA
8406602QA
8406602XA
8406602XA
*Add “96” suffix to part number for tape and reel packaging.
TEMP.
RANGE (°C)
0 to +70
PACKAGE
40 Ld PDIP
0 to +70
-40 to +85
-40 to +85
0 to +70
40 Ld PDIP (Pb-free)
40 Ld PDIP
40 Ld PDIP (Pb-free)
44 Ld PLCC
0 to +70
-40 to +85
-40 to +85
0 to +70
-40 to +85
-40 to +85
-55 to +125
SMD#
SMD#
44 Ld PLCC (Pb-free)
44 Ld PLCC
44 Ld PLCC (Pb-free)
44 Ld MQFP (Pb-free)
44 Ld MQFP (Pb-free)
40 Ld CERDIP
44 Ld CLCC
PKG. DWG. #
E40.6
N44.65
Q44.10x10
F40.6
J44.A
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2002, 2005, 2006, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.






82C55A Datasheet, Funktion
82C55A
The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions. All of the output registers,
including the status flip-flops, will be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be “tailored” to almost any I/O
structure. For instance: Group B can be programmed in
Mode 0 to monitor simple switch closings or display
computational results, Group A could be programmed in
Mode 1 to monitor a keyboard or tape reader on an interrupt-
driven basis.
The mode definitions and possible mode combinations may
seem confusing at first, but after a cursory review of the
complete device operation a simple, logical I/O approach will
surface. The design of the 82C55A has taken into account
things such as efficient PC board layout, control signal
definition vs. PC layout and complete functional flexibility to
support almost any peripheral device with no external logic.
Such design represents the maximum use of the available
pins.
Single Bit Set/Reset Feature (Figure 5)
Any of the eight bits of Port C can be Set or Reset using a
single Output instruction. This feature reduces software
requirements in control-based applications.
When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset
operation just as if they were output ports.
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
XX X
DON’T
CARE
BIT SET/RESET
1 = SET
0 = RESET
BIT SELECT
01234567
0 1 0 1 0 1 0 1 B0
0 0 1 1 0 0 1 1 B1
0 0 0 0 1 1 1 1 B2
BIT SET/RESET FLAG
0 = ACTIVE
FIGURE 5. BIT SET/RESET FORMAT
Interrupt Control Functions
When the 82C55A is programmed to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request
signals, generated from port C, can be inhibited or enabled
by setting or resetting the associated INTE flip-flop, using
the bit set/reset function of port C.
This function allows the programmer to enable or disable a
CPU interrupt by a specific I/O device without affecting any
other device in the interrupt structure.
INTE Flip-Flop Definition
(BIT-SET)-INTE is SET - Interrupt Enable
(BIT-RESET)-INTE is Reset - Interrupt Disable
NOTE: All Mask flip-flops are automatically reset during mode
selection and device Reset.
Operating Modes
Mode 0 (Basic Input/Output). This functional configuration
provides simple input and output operations for each of the
three ports. No handshaking is required, data is simply
written to or read from a specific port.
Mode 0 Basic Functional Definitions:
• Two 8-bit ports and two 4-bit ports
• Any Port can be input or output
• Outputs are latched
• Inputs are not latched
• 16 different Input/Output configurations possible
A
D4 D3
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
MODE 0 PORT DEFINITION
B GROUP A
GROUP B
PORT C
PORT C
D1 D0 PORT A (Upper) # PORT B (Lower)
0 0 Output Output 0 Output Output
0 1 Output Output 1 Output Input
1 0 Output Output 2 Input Output
1 1 Output Output 3 Input Input
0 0 Output Input 4 Output Output
0 1 Output Input 5 Output Input
1 0 Output Input 6 Input Output
1 1 Output Input 7 Input Input
0 0 Input Output 8 Output Output
0 1 Input Output 9 Output Input
1 0 Input Output 10 Input Output
1 1 Input Output 11 Input Input
0 0 Input Input 12 Output Output
0 1 Input Input 13 Output Input
1 0 Input Input 14 Input Output
1 1 Input Input 15 Input Input
6 FN2969.11
December 8, 2015

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82C55A pdf, datenblatt
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
11
1/0 1/0 1/0
82C55A
PC2-PC0
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
GROUP B MODE
0 = MODE 0
1 = MODE 1
FIGURE 11. MODE CONTROL WORD
WR
RD
PC3
INTRA
PA7-PA0 8
INTE
1
PC7
PC6
OBFA
ACKA
INTE
2
PC4
PC5
STBA
IBFA
PC2-PC0
3
I/O
FIGURE 12. MODE 2
DATA FROM
CPU TO 82C55A
WR
OBF
INTR
ACK
STB
tWOB
tST
tAOB
tAK
IBF
PERIPHERAL
BUS
tSIB
tPS
tPH
tAD tKD
tRIB
RD
DATA FROM
DATA FROM
PERIPHERAL TO 82C55A
82C55A TO PERIPHERAL
DATA FROM
82C55A TO CPU
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF MASK STB RD + OBF MASK
ACK WR)
FIGURE 13. MODE 2 (BIDIRECTIONAL)
12 FN2969.11
December 8, 2015

12 Page





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