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PDF 82C55 Data sheet ( Hoja de datos )
| Número de pieza | 82C55 | |
| Descripción | CHMOS PROGRAMMABLE PERIPHERAL INTERFACE | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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82C55A
CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
Y Compatible with all Intel and Most
Other Microprocessors
Y High Speed ‘‘Zero Wait State’’
Operation with 8 MHz 8086 88 and
80186 188
Y 24 Programmable I O Pins
Y Low Power CHMOS
Y Completely TTL Compatible
Y Control Word Read-Back Capability
Y Direct Bit Set Reset Capability
Y 2 5 mA DC Drive Capability on all I O
Port Outputs
Y Available in 40-Pin DIP and 44-Pin PLCC
Y Available in EXPRESS
Standard Temperature Range
Extended Temperature Range
The Intel 82C55A is a high-performance CHMOS version of the industry standard 8255A general purpose
programmable I O device which is designed for use with all Intel and most other microprocessors It provides
24 I O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation
The 82C55A is pin compatible with the NMOS 8255A and 8255A-5
In MODE 0 each group of 12 I O pins may be programmed in sets of 4 and 8 to be inputs or outputs In
MODE 1 each group may be programmed to have 8 lines of input or output 3 of the remaining 4 pins are used
for handshaking and interrupt control signals MODE 2 is a strobed bi-directional bus configuration
The 82C55A is fabricated on Intel’s advanced CHMOS III technology which provides low power consumption
with performance equal to or greater than the equivalent NMOS product The 82C55A is available in 40-pin
DIP and 44-pin plastic leaded chip carrier (PLCC) packages
231256 – 31
Figure 1 82C55A Block Diagram
231256 – 1
231256 – 2
Figure 2 82C55A Pinout
Diagrams are for pin reference only Package
sizes are not to scale
October 1995
Order Number 231256-004
1 page  
82C55A
82C55A OPERATIONAL DESCRIPTION
Mode Selection
There are three basic modes of operation that can
be selected by the system software
Mode 0
Mode 1
Mode 2
Basic input output
Strobed Input output
Bi-directional Bus
When the reset input goes ‘‘high’’ all ports will be set
to the input mode with all 24 port lines held at a logic
‘‘one’’ level by the internal bus hold devices (see
Figure 4 Note) After the reset is removed the
82C55A can remain in the input mode with no addi-
tional initialization required This eliminates the need
for pullup or pulldown devices in ‘‘all CMOS’’ de-
signs During the execution of the system program
any of the other modes may be selected by using a
single output instruction This allows a single
82C55A to service a variety of peripheral devices
with a simple software maintenance routine
The modes for Port A and Port B can be separately
defined while Port C is divided into two portions as
required by the Port A and Port B definitions All of
the output registers including the status flip-flops
will be reset whenever the mode is changed Modes
may be combined so that their functional definition
can be ‘‘tailored’’ to almost any I O structure For
instance Group B can be programmed in Mode 0 to
monitor simple switch closings or display computa-
tional results Group A could be programmed in
Mode 1 to monitor a keyboard or tape reader on an
interrupt-driven basis
231256 – 6
Figure 6 Mode Definition Format
The mode definitions and possible mode combina-
tions may seem confusing at first but after a cursory
review of the complete device operation a simple
logical I O approach will surface The design of the
82C55A has taken into account things such as effi-
cient PC board layout control signal definition vs PC
layout and complete functional flexibility to support
almost any peripheral device with no external logic
Such design represents the maximum use of the
available pins
231256 –5
Figure 5 Basic Mode Definitions and Bus
Interface
Single Bit Set Reset Feature
Any of the eight bits of Port C can be Set or Reset
using a single OUTput instruction This feature re-
duces software requirements in Control-based appli-
cations
When Port C is being used as status control for Port
A or B these bits can be set or reset by using the Bit
Set Reset operation just as if they were data output
ports
5
5 Page 
Input Control Signal Definition
STB (Strobe Input) A ‘‘low’’ on this input loads
data into the input latch
IBF (Input Buffer Full F F)
A ‘‘high’’ on this output indicates that the data has
been loaded into the input latch in essence an ac-
knowledgement IBF is set by STB input being low
and is reset by the rising edge of the RD input
INTR (Interrupt Request)
A ‘‘high’’ on this output can be used to interrupt the
CPU when an input device is requesting service
INTR is set by the STB is a ‘‘one’’ IBF is a ‘‘one’’
and INTE is a ‘‘one’’ It is reset by the falling edge of
RD This procedure allows an input device to re-
quest service from the CPU by simply strobing its
data into the port
INTE A
Controlled by bit set reset of PC4
INTE B
Controlled by bit set reset of PC2
82C55A
231256 – 13
Figure 8 MODE 1 Input
Figure 9 MODE 1 (Strobed Input)
231256 – 14
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet 82C55.PDF ] | |
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