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PDF 82C54 Data sheet ( Hoja de datos )
| Número de pieza | 82C54 | |
| Descripción | CHMOS PROGRAMMABLE INTERVAL TIMER | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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82C54
CHMOS PROGRAMMABLE INTERVAL TIMER
Y Compatible with all Intel and most
other microprocessors
Y High Speed ‘‘Zero Wait State’’
Operation with 8 MHz 8086 88 and
80186 188
Y Handles Inputs from DC
10 MHz for 82C54-2
Y Available in EXPRESS
Standard Temperature Range
Extended Temperature Range
Y Three independent 16-bit counters
Y Low Power CHMOS
ICC e 10 mA 8 MHz Count
frequency
Y Completely TTL Compatible
Y Six Programmable Counter Modes
Y Binary or BCD counting
Y Status Read Back Command
Y Available in 24-Pin DIP and 28-Pin PLCC
The Intel 82C54 is a high-performance CHMOS version of the industry standard 8254 counter timer which is
designed to solve the timing control problems common in microcomputer system design It provides three
independent 16-bit counters each capable of handling clock inputs up to 10 MHz All modes are software
programmable The 82C54 is pin compatible with the HMOS 8254 and is a superset of the 8253
Six programmable timer modes allow the 82C54 to be used as an event counter elapsed time indicator
programmable one-shot and in many other applications
The 82C54 is fabricated on Intel’s advanced CHMOS III technology which provides low power consumption
with performance equal to or greater than the equivalent HMOS product The 82C54 is available in 24-pin DIP
and 28-pin plastic leaded chip carrier (PLCC) packages
231244 – 3
PLASTIC LEADED CHIP CARRIER
231244 –1
Figure 1 82C54 Block Diagram
October 1994
231244 – 2
Diagrams are for pin reference only
Package sizes are not to scale
Figure 2 82C54 Pinout
Order Number 231244-006
1 page  
82C54
OPERATIONAL DESCRIPTION
General
After power-up the state of the 82C54 is undefined
The Mode count value and output of all Counters
are undefined
How each Counter operates is determined when it is
programmed Each Counter must be programmed
before it can be used Unused counters need not be
programmed
Programming the 82C54
Counters are programmed by writing a Control Word
and then an initial count The control word format is
shown in Figure 7
All Control Words are written into the Control Word
Register which is selected when A1 A0 e 11 The
Control Word itself specifies which Counter is being
programmed
By contrast initial counts are written into the Coun-
ters not the Control Word Register The A1 A0 in-
puts are used to select the Counter to be written
into The format of the initial count is determined by
the Control Word used
Control Word Format
A1 A0 e 11 CS e 0 RD e 1 WR e 0
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD
SC Select Counter
SC1 SC0
0 0 Select Counter 0
0 1 Select Counter 1
1 0 Select Counter 2
1
1
Read-Back Command
(See Read Operations)
RW Read Write
RW1 RW0
0 0 Counter Latch Command (see Read
Operations)
0 1 Read Write least significant byte only
1 0 Read Write most significant byte only
1 1 Read Write least significant byte first
then most significant byte
NOTE Don’t care bits (X) should be 0 to insure
compatibility with future Intel products
M MODE
M2 M1
M0
0 0 0 Mode 0
0 0 1 Mode 1
X 1 0 Mode 2
X 1 1 Mode 3
1 0 0 Mode 4
1 0 1 Mode 5
BCD
0
1
Binary Counter 16-bits
Binary Coded Decimal (BCD) Counter
(4 Decades)
Figure 7 Control Word Format
5
5 Page 
82C54
MODE 2 RATE GENERATOR
This Mode functions like a divide-by-N counter It is
typicially used to generate a Real Time Clock inter-
rupt OUT will initially be high When the initial count
has decremented to 1 OUT goes low for one CLK
pulse OUT then goes high again the Counter re-
loads the initial count and the process is repeated
Mode 2 is periodic the same sequence is repeated
indefinitely For an initial count of N the sequence
repeats every N CLK cycles
GATE e 1 enables counting GATE e 0 disables
counting If GATE goes low during an output pulse
OUT is set high immediately A trigger reloads the
Counter with the initial count on the next CLK pulse
OUT goes low N CLK pulses after the trigger Thus
the GATE input can be used to synchronize the
Counter
After writing a Control Word and initial count the
Counter will be loaded on the next CLK pulse OUT
goes low N CLK Pulses after the initial count is writ-
ten This allows the Counter to be synchronized by
software also
231244 – 10
NOTE
A GATE transition should not occur one clock prior to
terminal count
Figure 17 Mode 2
Writing a new count while counting does not affect
the current counting sequence If a trigger is re-
ceived after writing a new count but before the end
of the current period the Counter will be loaded with
the new count on the next CLK pulse and counting
will continue from the new count Otherwise the
new count will be loaded at the end of the current
counting cycle In mode 2 a COUNT of 1 is illegal
MODE 3 SQUARE WAVE MODE
Mode 3 is typically used for Baud rate generation
Mode 3 is similar to Mode 2 except for the duty cycle
of OUT OUT will initially be high When half the ini-
tial count has expired OUT goes low for the remain-
der of the count Mode 3 is periodic the sequence
above is repeated indefinitely An initial count of N
results in a square wave with a period of N CLK
cycles
GATE e 1 enables counting GATE e 0 disables
counting If GATE goes low while OUT is low OUT is
set high immediately no CLK pulse is required A
trigger reloads the Counter with the initial count on
the next CLK pulse Thus the GATE input can be
used to synchronize the Counter
After writing a Control Word and initial count the
Counter will be loaded on the next CLK pulse This
allows the Counter to be synchronized by software
also
Writing a new count while counting does not affect
the current counting sequence If a trigger is re-
ceived after writing a new count but before the end
of the current half-cycle of the square wave the
Counter will be loaded with the new count on the
next CLK pulse and counting will continue from the
new count Otherwise the new count will be loaded
at the end of the current half-cycle
Mode 3 is implemented as follows
Even counts OUT is initially high The initial count is
loaded on one CLK pulse and then is decremented
by two on succeeding CLK pulses When the count
expires OUT changes value and the Counter is re-
loaded with the initial count The above process is
repeated indefinitely
Odd counts OUT is initially high The initial count
minus one (an even number) is loaded on one CLK
pulse and then is decremented by two on succeed-
ing CLK pulses One CLK pulse after the count ex-
pires OUT goes low and the Counter is reloaded
with the initial count minus one Succeeding CLK
pulses decrement the count by two When the count
expires OUT goes high again and the Counter is
reloaded with the initial count minus one The above
process is repeated indefinitely So for odd counts
11
11 Page | ||
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| PDF Descargar | [ Datasheet 82C54.PDF ] | |
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