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82C50A Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer 82C50A
Beschreibung CMOS Asynchronous Communications Element
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 21 Seiten
82C50A Datasheet, Funktion
82C50A
March 1997
CMOS Asynchronous
Communications Element
Features
• Single Chip UART/BRG
• DC to 625K Baud (DC to 10MHz Clock)
• Crystal or External Clock Input
• On Chip Baud Rate Generator 1 to 65535 Divisor
Generates 16X Clock
• Prioritized Interrupt Mode
• Fully TTL/CMOS Compatible
• Microprocessor Bus Oriented Interface
• 80C86/80C88 Compatible
• Scaled SAJI IV CMOS Process
• Low Power - 1mA/MHz Typical
• Modem Interface
• Line Break Generation and Detection
• Loopback and Echo Modes
• Doubled Buffered Transmitter and Receiver
• Single 5V Supply
Ordering Information
PACKAGE
PDIP
PLCC
CERDIP
TEMPERATURE
RANGE (oC)
0 to +70
-40 to +85
0 to +70
-40 to +85
0 to +70
-40 to +85
-55 to +125
625K BAUD
CP82C50A-5
IP82C50A-5
CS82C50A-5
IS82C50A-5
CD82C50A-5
ID82C50A-5
MD82C50A-5/B
PKG.
NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
Description
The 82C50A Asynchronous Communication Element (ACE)
is a high performance programmable Universal Asynchro-
nous Receiver/Transmitter (UART) and Baud Rate Genera-
tor (BRG) on a single chip. Using Intersil’s advanced Scaled
SAJI IV CMOS Process, the ACE will support data rates
from DC to 625K baud (0-10MHz clock).
The ACE’s receiver circuitry converts start, data, stop, and
parity bits into a parallel data word. The transmitter circuitry
converts a parallel data word into serial form and appends
the start, parity, and stop bits. The word length is program-
mable to 5, 6, 7, or 8 data bits. Stop bit selection provides a
choice of 1,1.5, or 2 stop bits.
The Baud Rate Generator divides the clock by a divisor
programmable from 1 to 216-1 to provide standard RS-232C
baud rates when using any one of three industry standard
baud rate crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).
A programmable buffered clock output (BAUDOUT) provides
either a buffered oscillator or 16X (16 times the data rate)
baud rate clock for general purpose system use.
To meet the system requirements of a CPU interfacing to an
asynchronous channel, the modem control signals RTS,
CTS, DSR, DTR, RI, DCD are provided. Inputs and outputs
have been designed with full TTL/CMOS compatibility in
order to facilitate mixed TTL/NMOS/CMOS system design.
Functional Diagram
CSO
CS1
CS2
12
13
14
ADS 25
A0 28
A1 27
A2 26
MR 35
DISTR 22
DISTR 21
DOSTR 19
DOSTR 18
D0 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
MICROPROCESSOR INTERFACE
24 CSOUT
23 DDIS
INTERRUPT 30 INTRPT
ENABLE,
ID, & CONTROL
UART
RECEIVER
LINE STATUS DIVISOR LATCH
AND CONTROL AND BAUD RATE
GENERATOR
TRANSMITTER
MODEM
MODEM CONTROL
MODEM STATUS
10 SIN
9 RCLK
15 BAUDOUT
16 XTAL1
17 XTAL2
11 SOUT
32 RTS
33 DTR
34 OUT1
31 OUT2
36 CTS
37 DSR
38 DCD
39 RI
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 2958.1






82C50A Datasheet, Funktion
82C50A
Accessible Registers
The three types of internal registers in the 82C50A used in
the operation of the device are control, status, and data
registers. The control registers are the Bit Rate Select
Register DLL and DLM, Line Control Register, Interrupt
Enable Register and the Modem Control registers, while the
status registers are the Line Status Registers and the
Modem Status Register. The data registers are the Receiver
Buffer Register and Transmitter Holding Register. The
Address, Read, and Write inputs are used in conjunction
with the Divisor Latch Access Bit in the Line Control Register
(LCR(7)) to select the register to be written or read (see
Table 1.). Individual bits within these registers are referred to
by the register mnemonic and the bit number in parenthesis.
An example, LCR(7) refers to Line Control Register Bit 7.
The Transmitter Buffer Register and Receiver Buffer Regis-
ter are data registers holding from 5-8 data bits. If less than
eight data bits are transmitted, data is right justified to the
LSB. Bit 0 of a data word is always the first serial data bit
received and transmitted. The 82C50A data registers are
double buffered so that read and write operations can be
performed at the same time the UART is performing the par-
allel to serial and serial to parallel conversion. This provides
the microprocessor with increased flexibility in its read and
write timing.
TABLE 1. ACCESSING 82C50A INTERNAL REGISTERS
DLAB A2 A1 A0 MNEMONIC
REGISTER
0 000
RBR
Receiver Buffer
Register (read only)
0 000
THR
Transmitter Holding
Register (write only)
0 001
lER Interrupt Enable
Register
X 010
IIR Interrupt Identifica-
tion Register
(read only)
X 011
LCR
Line Control Register
X 100
MCR
Modem Control
Register
X 101
LSR Line Status Register
X 110
MSR
Modem Status
Register
X 111
SCR
Scratch Register
1 000
DLL Divisor Latch (LSB)
1 001
DLM
Divisor Latch (MSB)
NOTE: X = “Don’t Care”, 0 = Logic Low, 1 = Logic High
Line Control Register (LCR)
LCR LCR LCR LCR LCR LCR LCR LCR
76543210
Word
Length
Select
0 0 = 5 Data Bits
0 1 = 6 Data Bits
1 0 = 7 Data Bits
1 1 = 8 Data Bits
Stop
Bit
Select
0 = 1 Stop Bit
1 = 1.5 Stop Bits if 5 Data Bit Word Length is Selected 2 Stop Bits if
6, 7, or 8 Data Bit Word Length is Selected
Parity
Enable
0 = Parity Disabled
1 = Parity Enabled (Generated & Checked)
Even Parity 0 = Odd Parity When Parity is Enabled
Select
1 = Even Parity When Parity is Enabled
Stick Parity
0 = Stick Parity Disabled
1 = When Parity is Enabled Forces the Transmission and Checking
of a Parity Bit of a Known State. Parity Bit Forced to a Logic 1 if
LCR (4) = 0 or to a Logic 0 If LCR (4) = 1.
Break
Control
0 = Break Disabled
1 = Break Enabled. The Serial Output (SOUT) is Forced to the
Spacing (Logic 0) State.
Divisor
Latch
Access Bit
0 = Must be Low to Access the Receiver Buffer. Transmitter Holding
Register or the Interrupt Enable Register.
1 = Must be High to Access the Divisor Latches DLL and DLM of the
Baud Rate Generator During a Read or Write Operation.
6

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82C50A pdf, datenblatt
82C50A
Modem Status Registers. The contents of the Interrupt
Enable Register are indicated in Table 3 and are described
below.
IER(0): When programmed high (IER(0) = Logic 1), IER(0)
enables Received Data Available interrupt.
IER(1): When programmed high (IER(1) = Logic 1), IER(1)
enables the Transmitter Holding Register Empty interrupt.
IER(2): When Programmed high (IER(2) = Logic 1), IER(2)
enables the Receiver Line Status interrupt.
IER(3): When programmed high (IER(3) = Logic 1), IER(3)
enables the Modem Status interrupt.
IER(4) - IER(7): These four bits of the IER are logic 0.
DR (LSR BIT 0)
ERBFI (IER BIT 0)
THRE (LSR BIT 5)
ETBEI (IER BIT 1)
OE (LSR BIT 1)
PE (LSR BIT 2)
INTRPT
PIN 30
FE (LSR BIT 3)
BI (LSR BIT 4)
ELSI (IER BIT 2)
DCTS (MSR BIT 0)
DDSR (MSR BIT 1)
TERI (MSR BIT 2)
DDCD (MSR BIT 3)
EDSSI (IER BIT 3)
FIGURE 1. 82C50A INTERRUPT CONTROL STRUCTURE
REGISTER
MNEMONIC
RBR
(Read Only)
THR
(Write Only)
DLL
DLM
IER
BIT 7
Data Bit 7
(MSB)
Data Bit 7
Bit 7
Bit 15
0
IIR
(Read Only)
0
TABLE 3. 82C50A ACCESSIBLE REGISTER SUMMARY
(NOTE: See Table 1 for how to access these registers.)
BIT 6
Data Bit 6
BIT 5
Data Bit 5
REGISTER BIT NUMBER
BIT 4
BIT 3
Data Bit 4 Data Bit 3
BIT 2
Data Bit 2
BIT 1
Data Bit 1
Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1
Bit 6
Bit 14
0
0
Bit 5
Bit 13
0
0
Bit 4
Bit 12
0
0
Bit 3
Bit 11
(EDSSI)
Enable
Modem
Status
Interrupt
0
Bit 2
Bit 10
(ELSI)
Enable
Receiver
Line
Status
Interrupt
Interrupt ID
Bit (1)
Bit 1
Bit 9
(ETBEI)
Enable
Transmitter
Holding
Register
Empty
Interrupt
Interrupt ID
Bit (0)
LCR
MCR
(DLAB)
Divisor
Latch
Access
Bit
0
Set Break
Stick Parity
(EPS)
Even Parity
Select
(PEN)
Parity
Enable
0
0
Loop
Out 2
(STB)
Number
of Stop
Bits
Out 1
(WLSB1)
Word
Length
Select
Bit 1
(RTS)
Request
to Send
LSR
MSR
0
(DCD)
Data
Carrier
Detect
(TEMT)
Transmitter
Empty
(RI)
Ring
Indicator
(THRE)
Transmitter
Holding
Register
Empty
(DSR)
Data
Set
Ready
(BI)
Break
Interrupt
(CTS)
Clear
to
Send
SCR
Bit 7
Bit 6
Bit 5
LSB, Data Bit 0 is the first bit transmitted or received.
Bit 4
(FE)
Framing
Error
(DDCD)
Delta
Data
Carrier
Detect
Bit 3
(PE)
Parity
Error
(TERI)
Trailing
Edge
Ring
Indicator
Bit 2
(OE)
Overrun
Error
(DDSR)
Delta
Data
Set
Ready
Bit 1
BIT 0
Data Bit 0
(LSB)
Data Bit 0
Bit 0
Bit 8
(ERBFI)
Enable
Received
Data
Available
Interrupt
“0” 1F
Interrupt
Pending
(WLSB0)
Word
Length
Select
Bit 0
(DTR)
Data
Terminal
Ready
(DR)
Data
Ready
(DCTS)
Delta
Clear
to
Send
Bit 0
12

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