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PDF 82596DX Data sheet ( Hoja de datos )
| Número de pieza | 82596DX | |
| Descripción | HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR | |
| Fabricantes | Intel Corporation | |
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82596DX AND 82596SX
HIGH-PERFORMANCE 32-BIT LOCAL
AREA NETWORK COPROCESSOR
Y Performs Complete CSMA CD Medium
Access Control (MAC) Functions
Independently of CPU
IEEE 802 3 (EOC) Frame Delimiting
Y Supports Industry Standard LANs
IEEE TYPE 10BASE-T (TPE)
IEEE TYPE 10BASE5 (Ethernet )
IEEE TYPE 10BASE2 (Cheapernet)
IEEE TYPE 1BASE5 (StarLAN)
and the Proposed Standard
TYPE 10BASE-F
Proprietary CSMA CD Networks Up
to 20 Mb s
Y On-Chip Memory Management
Automatic Buffer Chaining
Buffer Reclamation after Receipt of
Bad Frames Optional Save Bad
Frames
32-Bit Segmented or Linear (Flat)
Memory Addressing Formats
Y 82586 Software Compatible
Y Optimized CPU Interface
82596DX Bus Interface Optimized to
Intel’s 32-Bit i386TMDX
82596SX Bus Interface Optimized to
Intel’s 16-Bit i386TMSX
Supports Big Endian and Little
Endian Byte Ordering
Y High-Performance 16- 32-Bit Bus
Master Interface
66-MB s Bus Bandwidth
33-MHz Clock Two Clocks Per
Transfer
Bus Throttle Timers
Transfers Data at 100% of Serial
Bandwidth
128-Byte Receive FIFO 64-Byte
Transmit FIFO
Y Network Management and Diagnostics
Monitor Mode
32-Bit Statistical Counters
Y Self-Test Diagnostics
Y Configurable Initialization Root for Data
Structures
Y High-Speed 5-V CHMOS IV
Technology
Y 132-Pin Plastic Quad Flat Pack (PQFP)
and PGA Package
(See Packaging Specifications Order Number 240800-001
Package Type KU and A)
i386TM is a trademark of Intel Corporation
Ethernet is a registered trademark of Xerox Corporation
CHMOS is a patented process of Intel Corporation
Figure 1 82596DX SX Block Diagram
290219 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
November 1995
Order Number 290219-006
1 page  
82596DX SX
Figure 2b 82596SX PQFP Pin Configuration
290219 – 34
5
5 Page 
82596DX SX
PIN DESCRIPTIONS (Continued)
Symbol
PQFP
Pin No
Type
Name and Function
WR
120 O WRITE READ This dual-function pin is used to distinguish Write and
Read cycles This line is floated after a Reset or when the bus is not
acquired
ADS
124 O ADDRESS STATUS This tri-state pin is used by the 82596 to indicate
that a valid bus cycle has begun and that A31 – A2 BE3 – BE0 and
W R are being driven It is asserted during t1 bus states This line is
floated after a Reset or when the bus is not acquired
RDY
130 I READY Active low This signal is the acknowledgment from
addressed memory that the transfer cycle can be completed When
high it causes wait states to be inserted It is ignored at the end of the
first clock of the bus cycle’s data cycle This active-low signal does not
have an internal pull-up resistor This signal must meet the setup and
hold times to operate correctly
LOCK 126 O LOCK This tri-state pin is used to distinguish locked and unlocked bus
cycles LOCK generates a semaphore handshake to the CPU LOCK
can be active for several memory cycles it goes active during the first
locked memory cycle (t1) and goes inactive at the last locked cycle
(t2) This line is floated after a Reset or when the bus is not acquired
LOCK can be disabled via the sysbus byte in software
BS16 129 I BUS SIZE This signal allows the 82596DX to work with either 16- or
32-bit bytes This signal is static and should be tied high for 32-bit
operation or low for 16-bit operation In Little Endian mode the D0 –
D15 lines are driven when BS16 is inserted in Big Endian mode the
D16–D31 lines are driven
HOLD 123 O HOLD The HOLD signal is active high the 82596 uses it to request
local bus mastership In normal operation HOLD goes inactive before
HLDA The 82596 can be forced off the bus by deasserting HLDA or if
the bus throttle timers expire
HLDA 118 I HOLD ACKNOWLEDGE The HLDA signal is active high it indicates
that bus mastership has been given to the 82596 HLDA is internally
synchronized after HOLD is detected low the CPU drives HLDA low
NOTE
Do not connect HLDA to VCC it will cause a deadlock A user wanting
to give the 82596 permanent access to the bus should connect HLDA
to HOLD If HLDA goes inactive before HOLD the 82596 will release
the bus (by deasserting HOLD) within a specified number of system
clocks
BREQ
115
I BUS REQUEST This signal when configured to an externally
activated mode is used to trigger the bus throttle timers
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 82596DX.PDF ] | |
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