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82503 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer 82503
Beschreibung DUAL SERIAL TRANSCEIVER (DST)
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 45 Seiten
82503 Datasheet, Funktion
82503
DUAL SERIAL TRANSCEIVER (DST)
82503 PRODUCT FEATURE SET OVERVIEW
Y Single Component Ethernet Interface
to Both 802 3 10BASE-T and AUI
Y Automatic or Manual Port Selection
Y Manchester Encoder Decoder and
Clock Recovery
Y No Glue Interface to Industry-Standard
LAN Controllers
Intel 82586 82590 82593 and 82596
AMD 7990 (LANCE )
National Semiconductor 8390 and
83932 (SONIC )
Western Digital 83C690
Fujitsu 86950 (Etherstar )
Y Diagnostic Loopback
Y Reset Low Power Modes
Y Network Status Indicators
Y Defeatable Jabber Timer
Y User Test Modes
Y 10 MHz Transmit Clock Generator
Y One Micron CHMOS IV (Px48)
Technology
Y Single 5-V Supply
INTERFACE FEATURES
TPE
Y Complies with 10BASE-T IEEE Std
802 3i-1990 for Twisted Pair Ethernet
Y Selectable Polarity Switching
Y Direct Interface to TPE Analog Filters
Y On-Chip TPE Squelch
Y Defeatable Link Integrity (LI)
Y Support of Cable Lengths l100m
AUI
Y Complies with IEEE 802 3 AUI Standard
Y Direct Interface to AUI Transformers
Y On-Chip AUI Squelch
A block diagram of a typical application is shown in Figure 1 The 82503 Dual Serial Transceiver is a high-inte-
gration CMOS device designed to simplify interfacing industry standard Ethernet LAN Controllers to IEEE
802 3 local area network applications (10BASE5 10BASE2 and 10BASE-T) The component supports both
an attachment unit interface (AUI) and a Twisted Pair Ethernet interface (TPE) It allows OEMs to design a
state-of-the-art media interface that is jumperless and fully automatic The 82503 includes on-chip AUI and
TPE drivers and receivers it offers designers a cost-effective integrated solution for interfacing LAN control-
lers to the wire medium
CHMOS is a patented process of Intel Corporation
Ethernet is a registered trademark of Xerox Corporation
LANCE is a registered trademark of Advanced Micro Devices
Etherstar is a registered trademark of Fujitsu Electronics
Sonic is a registered trademark of National Semiconductor Corporation
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
October 1995
Order Number 290421-004






82503 Datasheet, Funktion
82503
2 1 Power Pins
Symbol
PLCC
Pin
VSS(1)
VCC(1)
VCCA(1)
VSSA(1)
7 17 39
6 18 40
28
29
QFP
Pin
1 11 33
44 12 34
22
23
Type
Supply
Supply
Supply
Supply
Name and Function
Digital Ground
Digital VCC A 5-V g 5% Power Supply
Analog VCC A 5-V g 5% Power Supply
Analog Ground
NOTE
1 VCC and VCCA must be connected to the same power supply VSS and VSSA must be connected to the same ground
Separate decoupling and noise conditioning (e g ferrite beads) should be used
2 2 Clock Pins
Symbol
PLCC
Pin
QFP
Pin
X1 21 15
X2 20 14
Type
I
O
Name and Function
CLOCK CRYSTAL A 20 MHz crystal input This pin can be driven
with an external MOS level clock when X2 is left floating
CLOCK CRYSTAL A 20 MHz crystal output X1 can be driven with
an external MOS level clock when this pin is left floating
2 3 AUI Pins
Symbol
PLCC
Pin
TRMT
TRMT
27
26
RCV
RCV
31
30
CLSN
CLSN
25
24
QFP
Pin
21
20
25
24
19
18
Type
O
O
I
I
I
I
Name and Function
TRANSMIT PAIR A differential output driver pair that drives the
transmit pair of the transceiver cable The output bit stream is
Manchester encoded Following the last transition which is positive
at TRMT the differential voltage is reduced to zero volts
RECEIVE PAIR A differentially driven input pair which is tied to the
receive pair of the Ethernet transceiver cable The first transition on
RCV is negative-going to indicate the beginning of the frame The
last transition is positive-going to indicate the end of the frame The
received bit stream is assumed to be Manchester encoded
COLLISION PAIR A differentially driven input pair tied to the
collision presence pair of the Ethernet transceiver cable The
collision presence signal is a 10 MHz square wave The first
transition at CLSN is negative-going to indicate the beginning of the
signal the last transition is positive-going to indicate the end of the
signal
6

6 Page









82503 pdf, datenblatt
82503
Figure 6 Manchester Decoder and Clock Recovery
290421 – 5
3 3 2 AUI RECEIVE AND COLLISION BUFFERS
The AUI receive and collision inputs are driven
through isolation transformers to provide high volt-
age protection and DC common mode voltage rejec-
tion The incoming signals are converted to digital
levels and passed to the Manchester decoder and
collision detection circuitry
3 3 3 AUI RECEIVE AND COLLISION
SQUELCH CIRCUITS
Both the receive (RCV) and collision (CLSN) pairs
have the following squelch characteristics
 The squelch circuits are turned on at idle
 A pulse is rejected if the peak differential voltage
is more positive than b160 mV regardless of
pulse width
 A pulse is considered valid if its peak differential
voltage is more negative than b300 mV and its
width measured at b285 mV is greater than
25 ns
 The squelch circuits are disabled by the first valid
negative differential pulse on either the AUI re-
ceive (RCV) or the AUI collision (CLSN) pair
 If a positive differential pulse occurs on either the
AUI receive or collision pairs for greater than
160 ns End of Frame (EOF) is assumed and the
squelch circuitry is turned on
3 3 4 TPE RECEIVE BUFFER
The TPE receive pins (RD and RD) are connected to
the twisted pair medium through an analog front
end The analog front end contains the line coupling
devices and EMI filters necessary to conform to the
10BASE-T standards and local RF regulations The
input differential voltage range for the TPE receiver
is greater than 500 mV and less than 3 1V differen-
tial
3 3 5 TPE RECEIVE SQUELCH CIRCUITS
The TPE receive buffer distinguishes valid receive
differential data link test pulses and the idle condi-
tion according to the requirements of the 10BASE-T
standard Signals at the output of the EMI filter (thus
at the RD and RD pair) are rejected as follows
 All differential pulses of peak magnitude less than
300 mV are rejected
 All continuous sinusoids with a differential ampli-
tude less than 6 2 VPP and a frequency less than
2 MHz are rejected
 All sine waves of single cycle duration starting
with phase 0 or 180 that have an amplitude less
than 6 2 VPP and a frequency of 2 MHz to
16 MHz are rejected if the single cycle is pre-
ceeded and followed by 4 bit times of silence
(i e a signal less than 300 mV)
3 3 6 TPE Extended Squelch Mode
By placing the 82503 into TPE extended squelch
mode the 82503 can support cable lengths greater
than the 100m specified in the 10Base-T IEEE stan-
dard (802 3i-1990) The squelch thresholds for the
signals at the RD RD pair are typically reduced by
4 5 dB This allows Grade 5 twisted-pair cable to be
used to overcome attenuation and multipair cross-
talk for cable lengths up to 200 meters
12

12 Page





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