82375SB Datasheet PDF - Intel Corporation
| Part Number | 82375SB | |
| Description | PCI-EISA BRIDGE (PCEB) | |
| Manufacturers | Intel Corporation | |
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There is a preview and 82375SB download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
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82375EB 82375SB PCI-EISA BRIDGE (PCEB)
Y Provides the Bridge Between the PCI
Local Bus and EISA Bus
Y 100% PCI and EISA Compatible
PCI and EISA Master Slave Interface
Directly Drives 10 PCI Loads and 8
EISA Slots
Supports PCI from 25 to 33 MHz
Y Data Buffers Improve Performance
Four 32-bit PCI-to-EISA Posted Write
Buffers
Four 16-byte EISA-to-PCI Read Write
Line Buffers
EISA-to-PCI Read Prefetch
EISA-to-PCI and PCI-to-EISA Write
Posting
Y Data Buffer Management Ensures Data
Coherency
Flush Posted Write Buffers
Flush or Invalidate Line Buffers
System-Wide Data Buffer Coherency
Control
Y Burst Transfers on both the PCI and
EISA Buses
Y 32-Bit Data Paths
Y Integrated EISA Data Swap Buffers
Y Arbitration for PCI Devices
Supports Six PCI Masters
Fixed Rotating or a Combination of
the Two
Supports External PCI Arbiter and
Arbiter Cascading
Y PCI and EISA Address Decoding and
Mapping
Positive Decode of Main Memory
Areas (MEMCS Generation)
Four Programmable PCI Memory
Space Regions
Four Programmable PCI I O Space
Regions
Y Programmable Main Memory Address
Decoding
Main Memory Sizes up to
512 MBytes
Access Attributes for 15 Memory
Segments in First 1 MByte of Main
Memory
Programmable Main Memory Hole
Y Integrated 16-bit BIOS Timer
Y Only Available as Part of a Supported
Kit
The 82375EB SB PCI-EISA Bridge (PCEB) provides the master slave functions on both the PCI Local Bus
and the EISA Bus Functioning as a bridge between the PCI and EISA buses the PCEB provides the address
and data paths bus controls and bus protocol translation for PCI-to-EISA and EISA-to-PCI transfers Exten-
sive data buffering in both directions increases system performance by maximizing PCI and EISA Bus efficien-
cy and allowing concurrency on the two buses The PCEB’s buffer management mechanism ensures data
coherency The PCEB integrates central bus control functions including a programmable bus arbiter for the
PCI Bus and EISA data swap buffers for the EISA Bus Integrated system functions include PCI parity genera-
tion system error reporting and programmable PCI and EISA memory and I O address space mapping and
decoding The PCEB also contains a BIOS Timer that can be used to implement timing loops The PCEB is
intended to be used with the EISA System Component (ESC) to provide an EISA I O subsystem interface
This document describes both the 82375EB and 82375SB components Unshaded areas describe the
82375EB Shaded areas like this one describe the 82375SB operations that differ from the 82375EB
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
March 1996
Order Number 290477-004
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CONTENTS
5 1 2 9 Memory Read Line
5 1 2 10 Memory Write And Invalidate
5 1 3 PCI TRANSFER BASICS
5 1 3 1 Turn-Around-Cycle Definition
5 1 3 2 Idle Cycle Definition
5 1 4 BASIC READ
5 1 5 BASIC WRITE
5 1 6 CONFIGURATION CYCLES
5 1 7 INTERRUPT ACKNOWLEDGE CYCLE
5 1 8 EXCLUSIVE ACCESS
5 1 9 DEVICE SELECTION
5 1 10 TRANSACTION TERMINATION
5 1 10 1 Master Initiated Termination
5 1 10 2 Target Initiated Termination
5 1 10 3 PCEB Target Termination Conditions
5 1 10 4 PCEB Master Termination Conditions
5 1 10 5 PCEB Responses Results Of Termination
5 1 11 PCI DATA TRANSFERS WITH SPECIFIC BYTE ENABLE COMBINATIONS
5 2 PCI Bus Latency
5 2 1 MASTER LATENCY TIMER (MLT)
5 2 2 INCREMENTAL LATENCY MECHANISM
5 3 PCI Bus Parity Support And Error Reporting
5 3 1 PARITY GENERATION AND CHECKING
5 3 1 1 Address Phase
5 3 1 2 Data Phase
5 3 2 PARITY ERROR PERR SIGNAL
5 3 3 SYSTEM ERRORS
5 4 PCI Bus Arbitration
5 4 1 PCI ARBITER CONFIGURATION
5 4 1 1 Fixed Priority Mode
5 4 1 2 Rotating Priority Mode
5 4 1 3 Mixed Priority Mode
5 4 1 4 Locking Masters
5 4 2 ARBITRATION SIGNALING PROTOCOL
5 4 2 1 REQ and GNT Rules
5 4 2 2 Back-to-Back Transactions
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 82375SB electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Product Image and Detail view |  1. PCI-EISA Bridge (PCEB) - INTEL [ Learn More ] | |
| Download | [ 82375SB.PDF Datasheet ] | |
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