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Teilenummer | 81C55 |
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Beschreibung | 2048-Bit CMOS STATIC RAM WITH I/O PORTS AND TIMER | |
Hersteller | OKI electronic componets | |
Logo | ||
Gesamt 19 Seiten E2O0014-27-X2
¡ Semiconductor¡ Semiconductor
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Previous version: Aug. 1996
MSM81C55-5RS/GS/JS
2048-Bit CMOS STATIC RAM WITH I/O PORTS AND TIMER
GENERAL DESCRIPTION
The MSM81C55-5 has a 2k-bit static RAM (256 bytes) with parallel I/O ports and a timer. It uses
silicon gate CMOS technology and consumes a standby current of 100 micro ampere, maximum,
while the chip is not selected. Featureing a maximum access time of 400 ns, the MSM81C55-5
can be used in an MSM80C85AH system without using wait states. The parallel I/O consists
of two 8-bit ports and one 6-bit port (both general purpose).
The MSM81C55-5 also contains a 14-bit programmable counter/timer which may be used for
sequence-wave generation or terminal count-pulsing.
FEATURES
• High speed and low power achieved with silicon gate CMOS technology
• 256 words x 8bits RAM
• Single power supply, 3 to 6 V
• Completely static operation
• On-chip address latch
• 8-bit programmable I/O ports (port A and B)
• TTL Compatible
• RAM data hold characteristic at 2 V
• 6-bit programmable I/O port (port C)
• 14-bit programmable binary counter/timer
• Multiplexed address/data bus
• Direct interface with MSM80C85AH
• 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM81C55-5RS)
• 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM81C55-5JS)
• 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM81C55-5GS-2K)
FUNCTIONAL BLOCK DIAGRAM
IO/M
AD0 - 7
CE
ALE
RD
WR
RESET
256 ¥ 8
Static
RAM
Timer
Port A
A 8 PA0 - 7
Port B
B 8 PB0 - 7
Port C
C 6 PC0 - 5
TIMER IN
TIMER OUT
VCC (+5 V)
GND (0 V)
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¡ Semiconductor
Strobe Input Mode
BF
STROBE
INTR
RD
Input Data
From Port
tSBF
tSS tSI
tPSS tPHS
MSM81C55-5RS/GS/JS
tRBE
tRDI
Strobe Output Mode
BF
STROBE
INTR
WR
Output Data
To Port
tWBF
tWI
tWP
tSBE
tSI
6/19
6 Page ¡ Semiconductor
MSM81C55-5RS/GS/JS
(2) Reading the C/S Register
The I/O and timer status can be accessed by reading the contents of the Status register
located at I/O address xxxxx000. The status word format is shown below:
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
TIMER
INTE
B
B
BF
INTR INTE
BA
A
BF
INTR
A
Port A Interrupt Request
Port A Buffer Full
Port A Interrupt Enable
Port B Interrupt Request
Port B Buffer Full
Port B Interrupt Enable
Timer Interrupt. This bit is set high when the timer
reaches TC, and is reset when the C/S register is read
or a hardware reset occurs.
(3) PA and PB Registers
These registers may be used as either input or output ports depending on the programmed
contents of the C/S register. They may also be used either in the basic mode or in the strobe
mode.
I/O address of the PA register: xxxxx001
I/O address of the PB register: xxxxx010
(4) PC Register
The PC register may be used as an input port, output port or control register depending on
the programmed contents of the C/S register. The I/O address of the PC register is
xxxxx011.
(5) Timer
The timer is a 14-bit down counter which counts TIMER IN pulses.
The low order byte of the timer register has an I/O address of xxxxx100, and the high order
byte of the register has an I/O address of xxxxx101.
The count length register (CLR) may be preset with two bytes of data. Bits 0 through 13 are
assigned to the count length and bits 14 and 15 specify the timer output mode. A read
operation of the CLR reads the contents of the counter and the pertinent output mode. The
initial value range which can initially be loaded into the counter is 2 through 3FFF hex. Bit
assignments to the timer counter and possible output modes are shown in the following.
M2 M1 T13 T12 T11 T10 T9
T8
Output Mode
High Order 6 Bits of Count Length
T7 T6 T5 T4 T3 T2 T1 T0
Low Order Byte of Count Length
12/19
12 Page | ||
Seiten | Gesamt 19 Seiten | |
PDF Download | [ 81C55 Schematic.PDF ] |
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