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80L188EB Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer 80L188EB
Beschreibung 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 59 Seiten
80L188EB Datasheet, Funktion
80C186EB 80C188EB AND 80L186EB 80L188EB
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
X Full Static Operation
X True CMOS Inputs and Outputs
Y Integrated Feature Set
Low-Power Static CPU Core
Two Independent UARTs each with
an Integral Baud Rate Generator
Two 8-Bit Multiplexed I O Ports
Programmable Interrupt Controller
Three Programmable 16-Bit
Timer Counters
Clock Generator
Ten Programmable Chip Selects with
Integral Wait-State Generator
Memory Refresh Control Unit
System Level Testing Support (ONCE
Mode)
Y Direct Addressing Capability to 1 Mbyte
Memory and 64 Kbyte I O
Y Speed Versions Available (5V)
25 MHz (80C186EB25 80C188EB25)
20 MHz (80C186EB20 80C188EB20)
13 MHz (80C186EB13 80C188EB13)
Y Available in Extended Temperature
Range (b40 C to a85 C)
Y Speed Versions Available (3V)
16 MHz (80L186EB16 80L188EB16)
13 MHz (80L186EB13 80L188EB13)
Y Low-Power Operating Modes
Idle Mode Freezes CPU Clocks but
keeps Peripherals Active
Powerdown Mode Freezes All
Internal Clocks
Y Supports 80C187 Numeric Coprocessor
Interface (80C186EB PLCC Only)
Y Available In
80-Pin Quad Flat Pack (QFP)
84-Pin Plastic Leaded Chip Carrier
(PLCC)
80-Pin Shrink Quad Flat Pack (SQFP)
The 80C186EB is a second generation CHMOS High-Integration microprocessor It has features that are new
to the 80C186 family and include a STATIC CPU core an enhanced Chip Select decode unit two independent
Serial Channels I O ports and the capability of Idle or Powerdown low power modes
272433 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
June, 2002
Order Number: 272433-005
COPYRIGHT © INTEL CORPORATION, 2002






80L188EB Datasheet, Funktion
80C186EB 80C188EB 80L186EB 80L188EB
PCB
Offset
Function
00H Reserved
02H End Of Interrupt
04H Poll
06H Poll Status
08H Interrupt Mask
0AH Priority Mask
0CH
In-Service
0EH Interrupt Request
10H Interrupt Status
12H Timer Control
14H Serial Control
16H INT4 Control
18H INT0 Control
1AH INT1 Control
1CH INT2 Control
1EH INT3 Control
20H Reserved
22H Reserved
24H Reserved
26H Reserved
28H Reserved
2AH
Reserved
2CH
Reserved
2EH
Reserved
30H Timer0 Count
32H Timer0 Compare A
34H Timer0 Compare B
36H Timer0 Control
38H Timer1 Count
3AH Timer1 Compare A
3CH Timer1 Compare B
3EH Timer1 Control
PCB
Offset
Function
PCB
Offset
Function
40H Timer2 Count
80H GCS0 Start
42H Timer2 Compare 82H GCS0 Stop
44H Reserved
84H GCS1 Start
46H Timer2 Control
86H GCS1 Stop
48H Reserved
88H GCS2 Start
4AH
Reserved
8AH
GCS2 Stop
4CH
Reserved
8CH GCS3 Start
4EH
Reserved
8EH
GCS3 Stop
50H Port 1 Direction
90H GCS4 Start
52H Port 1 Pin
92H GCS4 Stop
54H Port 1 Control
94H GCS5 Start
56H Port 1 Latch
96H GCS5 Stop
58H Port 2 Direction
98H GCS6 Start
5AH
Port 2 Pin
9AH
GCS6 Stop
5CH Port 2 Control
9CH GCS7 Start
5EH Port 2 Latch
9EH
GCS7 Stop
60H Serial0 Baud
A0H
LCS Start
62H Serial0 Count
A2H
LCS Stop
64H Serial0 Control
A4H
UCS Start
66H Serial0 Status
A6H
UCS Stop
68H Serial0 RBUF
A8H
Relocation
6AH Serial0 TBUF
AAH
Reserved
6CH
Reserved
ACH
Reserved
6EH
Reserved
AEH
Reserved
70H Serial1 Baud
B0H Refresh Base
72H Serial1 Count
B2H Refresh Time
74H Serial1 Control
B4H Refresh Control
76H Serial1 Status
B6H
Reserved
78H Serial1 RBUF
B8H Power Control
7AH Serial1 TBUF
BAH
Reserved
7CH
Reserved
BCH
Step ID
7EH
Reserved
BEH
Reserved
Figure 3 Peripheral Control Block Registers
PCB
Offset
C0H
C2H
C4H
C6H
C8H
CAH
CCH
CEH
D0H
D2H
D4H
D6H
D8H
DAH
DCH
DEH
E0H
E2H
E4H
E6H
E8H
EAH
ECH
EEH
F0H
F2H
F4H
F6H
F8H
FAH
FCH
FEH
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6

6 Page









80L188EB pdf, datenblatt
80C186EB 80C188EB 80L186EB 80L188EB
Pin
Name
DT R
LOCK
HOLD
HLDA
NCS
(N C )
ERROR
(N C )
PEREQ
(N C )
UCS
LCS
P1 0 GCS0
P1 1 GCS1
P1 2 GCS2
P1 3 GCS3
P1 4 GCS4
P1 5 GCS5
P1 6 GCS6
P1 7 GCS7
Pin
Type
O
O
I
O
O
I
I
O
O
O
Input
Type
A(L)
A(L)
A(L)
Table 3 Pin Descriptions (Continued)
Output
States
Description
H(Z)
R(Z)
P(X)
Data Transmit Receive output controls the direction of a
bi-directional buffer in a buffered system DT R is only
available for the PLCC package
H(Z)
R(WH)
P(1)
LOCK output indicates that the bus cycle in progress is not
to be interrupted The processor will not service other bus
requests (such as HOLD) while LOCK is active This pin is
configured as a weakly held high input while RESIN is
active and must not be driven low
HOLD request input to signal that an external bus master
wishes to gain control of the local bus The processor will
relinquish control of the local bus between instruction
boundaries not conditioned by a LOCK prefix
H(1) HoLD Acknowledge output to indicate that the processor
R(0) has relinquished control of the local bus When HLDA is
P(0) asserted the processor will (or has) floated its data bus
and control signals allowing another bus master to drive the
signals directly
H(1) Numerics Coprocessor Select output is generated when
R(1) accessing a numerics coprocessor NCS is not provided on
P(1) the QFP or SQFP packages This signal does not exist on
the 80C188EB 80L188EB
ERROR input that indicates the last numerics coprocessor
operation resulted in an exception condition An interrupt
TYPE 16 is generated if ERROR is sampled active at the
beginning of a numerics operation ERROR is not provided
on the QFP or SQFP packages This signal does not exist
on the 80C188EB 80L188EB
CoProcessor REQuest signals that a data transfer
between an External Numerics Coprocessor and Memory is
pending PEREQ is not provided on the QFP or SQFP
packages This signal does not exist on the 80C188EB
80L188EB
H(1) Upper Chip Select will go active whenever the address of
R(1) a memory or I O bus cycle is within the address limitations
P(1) programmed by the user After reset UCS is configured to
be active for memory accesses between 0FFC00H and
0FFFFFH
H(1) Lower Chip Select will go active whenever the address of
R(1) a memory bus cycle is within the address limitations
P(1) programmed by the user LCS is inactive after a reset
H(X) H(1)
R(1)
P(X) P(1)
These pins provide a multiplexed function If enabled each
pin can provide a Generic Chip Select output which will go
active whenever the address of a memory or I O bus cycle
is within the address limitations programmed by the user
When not programmed as a Chip-Select each pin may be
used as a general purpose output Port As an output port
pin the value of the pin can be read internally
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
12

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