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80L186EC16 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer 80L186EC16
Beschreibung 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
80L186EC16 Datasheet, Funktion
80C186EC 80C188EC AND 80L186EC 80L188EC
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
X Fully Static Operation
X True CMOS Inputs and Outputs
Y Integrated Feature Set
Low-Power Static Enhanced 8086
CPU Core
Two Independent DMA Supported
UARTs each with an Integral Baud
Rate Generator
Four Independent DMA Channels
22 Multiplexed I O Port Pins
Two 8259A Compatible
Programmable Interrupt Controllers
Three Programmable 16-Bit Timer
Counters
32-Bit Watchdog Timer
Ten Programmable Chip Selects with
Integral Wait-State Generator
Memory Refresh Control Unit
Power Management Unit
On-Chip Oscillator
System Level Testing Support
(ONCE Mode)
Y Direct Addressing Capability to 1 Mbyte
Memory and 64 Kbyte I O
Y Low-Power Operating Modes
Idle Mode Freezes CPU Clocks but
Keeps Peripherals Active
Powerdown Mode Freezes All
Internal Clocks
Powersave Mode Divides All Clocks
by Programmable Prescalar
Y Available in Extended Temperature
Range (b40 C to a85 C)
Y Supports 80C187 Numerics Processor
Extension (80C186EC only)
Y Package Types
100-Pin EIAJ Quad Flat Pack (QFP)
100-Pin Plastic Quad Flat Pack
(PQFP)
100-Pin Shrink Quad Flat Pack
(SQFP)
Y Speed Versions Available (5V)
25 MHz (80C186EC25 80C188EC25)
20 MHz (80C186EC20 80C188EC20)
13 MHz (80C186EC13 80C188EC13)
Y Speed Version Available (3V)
16 MHz (80L186EC16 80L188EC16)
13 MHz (80L186EC13 80L188EC13)
The 80C186EC is a member of the 186 Integrated Processor Family The 186 Integrated Processor Family
incorporates several different VLSI devices all of which share a common CPU architecture the 8086 8088
The 80C186EC uses the latest high density CHMOS technology to integrate several of the most common
system peripherals with an enhanced 8086 CPU core to create a powerful system on a single monolithic
silicon die
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
May 1996
Order Number 272434-004






80L186EC16 Datasheet, Funktion
80C186EC 188EC 80L186EC 188EC
PCB
Offset
Function
00H Master PIC Port 0
02H Master PIC Port 1
04H Slave PIC Port 0
06H Slave PIC Port 1
08H Reserved
0AH SCU Int Req Ltch
0CH DMA Int Req Ltch
0EH TCU Int Req Ltch
10H Reserved
12H Reserved
14H Reserved
16H Reserved
18H Reserved
1AH Reserved
1CH
Reserved
1EH Reserved
20H WDT Reload High
22H WDT Reload Low
24H WDT Count High
26H WDT Count Low
28H WDT Clear
2AH WDT Disable
2CH
Reserved
2EH Reserved
30H T0 Count
32H T0 Compare A
34H T0 Compare B
46H T0 Control
38H T1 Count
3AH T1 Compare A
3CH T1 Compare B
3EH T1 Control
PCB
Offset
Function
PCB
Offset
Function
40H T2 Count
80H GCS0 Start
42H T2 Compare
82H GCS0 Stop
44H Reserved
84H GCS1 Start
46H T2 Control
86H GCS1 Stop
48H Port 3 Direction
88H GCS2 Start
4AH Port 3 Pin State
8AH GCS2 Stop
4CH Port 3 Mux Control
8CH
GCS3 Start
4EH Port 3 Data Latch
8EH
GCS3 Stop
50H Port 1 Direction
90H GCS4 Start
52H Port 1 Pin State
92H GCS4 Stop
54H Port 1 Mux Control 94H GCS5 Start
56H Port 1 Data Latch 96H GCS5 Stop
58H Port 2 Direction
98H GCS6 Start
5AH Port 2 Pin State
9AH GCS6 Stop
5CH Port 2 Mux Control
9CH
GCS7 Start
5EH Port 2 Data Latch
9EH
GCS7 Stop
60H SCU 0 Baud
A0H LCS Start
62H SCU 0 Count
A2H LCS Stop
64H SCU 0 Control
A4H UCS Start
66H SCU 0 Status
A6H UCS Stop
68H SCU 0 RBUF
A8H Relocation Register
6AH SCU 0 TBUF
AAH
Reserved
6CH
Reserved
ACH
Reserved
6EH Reserved
AEH
Reserved
70H SCU 1 Baud
B0H Refresh Base Addr
72H SCU 1 Count
B2H Refresh Time
74H SCU 1 Control
B4H Refresh Control
76H SCU 1 Status
B6H Refresh Address
78H SCU 1 RBUF
B8H Power Control
7AH SCU 1 TBUF
BAH
Reserved
7CH
Reserved
BCH
Step ID
7EH Reserved
BEH
Powersave
Figure 3 Peripheral Control Block Registers
PCB
Offset
Function
C0H DMA 0 Source Low
C2H DMA 0 Source High
C4H DMA 0 Dest Low
C6H DMA 0 Dest High
C8H DMA 0 Count
CAH DMA 0 Control
CCH DMA Module Pri
CEH
DMA Halt
D0H DMA 1 Source Low
D2H DMA 1 Source High
D4H DMA 1 Dest Low
D6H DMA 1 Dest High
D8H DMA 1 Count
DAH DMA 1 Control
DCH
Reserved
DEH
Reserved
E0H DMA 2 Source Low
E2H DMA 2 Source High
E4H DMA 2 Dest Low
E6H DMA 2 Dest High
E8H DMA 2 Count
EAH DMA 2 Control
ECH
Reserved
EEH
Reserved
F0H DMA 3 Source Low
F2H DMA 3 Source High
F4H DMA 3 Dest Low
F6H DMA 3 Dest High
F8H DMA 3 Count
FAH DMA 3 Control
FCH
Reserved
FEH
Reserved
6

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80L186EC16 pdf, datenblatt
80C186EC 188EC 80L186EC 188EC
Pin Name
RD
WR
READY
DEN
DT R
LOCK
HOLD
HLDA
NCS
ERROR
Pin
Type
O
O
I
O
O
IO
I
O
O
I
Input
Type
A(L)
S(L)
(Note 1)
A(L)
A(L)
A(L)
Table 2 Pin Descriptions (Continued)
Output
States
Pin Description
H(Z)
R(Z)
I(1)
P(1)
ReaD output signals that the accessed memory or I O
device should drive data information onto the data bus
H(Z)
R(Z)
I(1)
P(1)
WRite output signals that data available on the data bus are
to be written into the accessed memory or I O device
READY input to signal the completion of a bus cycle READY
must be active to terminate any 80C186EC bus cycle unless
it is ignored by correctly programming the Chip-Select unit
H(Z)
R(Z)
I(1)
P(1)
H(Z)
R(Z)
I(X)
P(X)
H(Z)
R(Z)
I(X)
P(X)
H(1)
R(0)
I(0)
P(0)
H(1)
R(1)
I(1)
P(1)
Data ENable output to control the enable of bi-directional
transceivers in a buffered system DEN is active only when
data is to be transferred on the bus
Data Transmit Receive output controls the direction of a bi-
directional buffer in a buffered system
LOCK output indicates that the bus cycle in progress is not
interruptable The processor will not service other bus
requests (such as HOLD) while LOCK is active This pin is
configured as a weakly held high input while RESIN is active
and must not be driven low
HOLD request input to signal that an external bus master
wishes to gain control of the local bus The processor will
relinquish control of the local bus between instruction
boundaries that are not LOCKed
HoLD Acknowledge output to indicate that the processor
has relinquished control of the local bus When HLDA is
asserted the processor will (or has) floated its data bus and
control signals allowing another bus master to drive the
signals directly
Numerics Coprocessor Select output is generated when
acessing a numerics coprocessor This signal does not exist
on the 80C188EC 80L188EC
ERROR input that indicates the last numerics processor
extension operation resulted in an exception condition An
interrupt TYPE 16 is generated if ERROR is sampled active
at the beginning of a numerics operation Systems not using
an 80C187 must tie ERROR to VCC This signal does not
exist on the 80C188EC 80L188EC
NOTE
Pin names in parentheses apply to the 80C188EC 80L188EC
12

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