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PDF 80C187 Data sheet ( Hoja de datos )
| Número de pieza | 80C187 | |
| Descripción | 80-BIT MATH COPROCESSOR | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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80C187
80-BIT MATH COPROCESSOR
Y High Performance 80-Bit Internal
Architecture
Y Implements ANSI IEEE Standard 754-
1985 for Binary Floating-Point
Arithmetic
Y Upward Object-Code Compatible from
8087
Y Fully Compatible with 387DX and 387SX
Math Coprocessors Implements all 387
Architectural Enhancements over 8087
Y Directly Interfaces with 80C186 CPU
Y 80C186 80C187 Provide a Software
Binary Compatible Upgrade from
80186 82188 8087 Systems
Y Expands 80C186’s Data Types to
Include 32- 64- 80-Bit Floating-Point
32- 64-Bit Integers and 18-Digit BCD
Operands
Y Directly Extends 80C186’s Instruction
Set to Trigonometric Logarithmic
Exponential and Arithmetic
Instructions for All Data Types
Y Full-Range Transcendental Operations
for SINE COSINE TANGENT
ARCTANGENT and LOGARITHM
Y Built-In Exception Handling
Y Eight 80-Bit Numeric Registers Usable
as Individually Addressable General
Registers or as a Register Stack
Y Available in 40-Pin CERDIP and 44-Pin
PLCC Package
(See Packaging Outlines and Dimensions Order 231369)
The Intel 80C187 is a high-performance math coprocessor that extends the architecture of the 80C186 with
floating-point extended integer and BCD data types A computing system that includes the 80C187 fully
conforms to the IEEE Floating-Point Standard The 80C187 adds over seventy mnemonics to the instruction
set of the 80C186 including support for arithmetic logarithmic exponential and trigonometric mathematical
operations The 80C187 is implemented with 1 5 micron high-speed CHMOS III technology and packaged in
both a 40-pin CERDIP and a 44-pin PLCC package The 80C187 is upward object-code compatible from the
8087 math coprocessor and will execute code written for the 80387DX and 80387SX math coprocessors
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1992
Order Number 270640-004
1 page  
80C187
The 80C187 register set can be accessed either as
a stack with instructions operating on the top one or
two stack elements or as individually addressable
registers The TOP field in the status word identifies
the current top-of-stack register A ‘‘push’’ operation
decrements TOP by one and loads a value into the
new top register A ‘‘pop’’ operation stores the value
from the current top register and then increments
TOP by one The 80C187 register stack grows
‘‘down’’ toward lower-addressed registers
Instructions may address the data registers either
implicitly or explicitly Many instructions operate on
the register at the TOP of the stack These instruc-
tions implicitly address the register at which TOP
points Other instructions allow the programmer to
explicitly specify which register to use This explicit
addressing is also relative to TOP
TAG WORD
The tag word marks the content of each numeric
data register as Figure 3 shows Each two-bit tag
represents one of the eight data registers The prin-
cipal function of the tag word is to optimize the
NPX’s performance and stack handling by making it
possible to distinguish between empty and nonemp-
ty register locations It also enables exception han-
dlers to identify special values (e g NaNs or denor-
mals) in the contents of a stack location without the
need to perform complex decoding of the actual
data
STATUS WORD
The 16-bit status word (in the status register) shown
in Figure 4 reflects the overall state of the 80C187 It
may be read and inspected by programs
Bit 15 the B-bit (busy bit) is included for 8087 com-
patibility only It always has the same value as the
ES bit (bit 7 of the status word) it does not indicate
the status of the BUSY output of 80C187
Bits 13 – 11 (TOP) point to the 80C187 register that
is the current top-of-stack
The four numeric condition code bits (C3 – C0) are
similar to the flags in a CPU instructions that per-
form arithmetic operations update these bits to re-
flect the outcome The effects of these instructions
on the condition code are summarized in Tables 2
through 5
Bit 7 is the error summary (ES) status bit This bit is
set if any unmasked exception bit is set it is clear
otherwise If this bit is set the ERROR signal is as-
serted
Bit 6 is the stack flag (SF) This bit is used to distin-
guish invalid operations due to stack overflow or un-
derflow from other kinds of invalid operations When
SF is set bit 9 (C1) distinguishes between stack
overflow (C1 e 1) and underflow (C1 e 0)
Figure 4 shows the six exception flags in bits 5 – 0 of
the status word Bits 5 – 0 are set to indicate that the
80C187 has detected an exception while executing
an instruction A later section entitled ‘‘Exception
Handling’’ explains how they are set and used
Note that when a new value is loaded into the status
word by the FLDENV or FRSTOR instruction the
value of ES (bit 7) and its reflection in the B-bit (bit
15) are not derived from the values loaded from
memory but rather are dependent upon the values of
the exception flags (bits 5 – 0) in the status word and
their corresponding masks in the control word If ES
is set in such a case the ERROR output of the
80C187 is activated immediately
15
TAG (7)
TAG (6)
TAG (5)
TAG (4)
TAG (3)
TAG (2)
TAG (1)
0
TAG (0)
NOTE
The index i of tag(i) is not top-relative A program typically uses the ‘‘top’’ field of Status Word to determine
which tag(i) field refers to logical top of stack
TAG VALUES
00 e Valid
01 e Zero
10 e QNaN SNaN Infinity Denormal and Unsupported Formats
11 e Empty
Figure 3 Tag Word
5
5 Page 
80C187
Exception
Invalid
Operation
Denormalized
Operand
Zero Divisor
Overflow
Underflow
Inexact
Result
(Precision)
Table 6 Exceptions
Cause
Operation on a signalling NaN
unsupported format indeterminate
form (0 % 0 0) (a %)
a (b %) etc ) or stack
overflow underflow (SF is also set)
At least one of the operands is
denormalized i e it has the smallest
exponent but a nonzero significand
The divisor is zero while the dividend
is a noninfinite nonzero number
The result is too large in magnitude
to fit in the specified format
The true result is nonzero but too small
to be represented in the specified format and
if underflow exception is masked denormalization
causes loss of accuracy
The true result is not exactly representable
in the specified format (e g 1 3)
the result is rounded according to the
rounding mode
Default Action
(If Exception is Masked)
Result is a quiet NaN
integer indefinite or
BCD indefinite
The operand is normalized
and normal processing
continues
Result is %
Result is largest finite
value or %
Result is denormalized
or zero
Normal processing
continues
Initialization
After FNINIT or RESET the control word contains
the value 037FH (all exceptions masked precision
control 64 bits rounding to nearest) the same values
as in an 8087 after RESET For compatibility with the
8087 the bit that used to indicate infinity control (bit
12) is set to zero however regardless of its setting
infinity is treated in the affine sense After FNINIT or
RESET the status word is initialized as follows
All exceptions are set to zero
Stack TOP is zero so that after the first push the
stack top will be register seven (111B)
The condition code C3 – C0 is undefined
The B-bit is zero
The tag word contains FFFFH (all stack locations
are empty)
80C186 80C187 initialization software should exe-
cute an FNINIT instruction (i e an FINIT without a
preceding WAIT) after RESET The FNINIT is not
strictly required for 80C187 software but Intel
recommends its use to help ensure upward compati-
bility with other processors
8087 Compatibility
This section summarizes the differences between
the 80C187 and the 8087 Many changes have been
designed into the 80C187 to directly support the
IEEE standard in hardware These changes result in
increased performance by elminating the need for
software that supports the standard
GENERAL DIFFERENCES
The 8087 instructions FENI FNENI and FDISI
FNDISI perform no useful function in the 80C187
Numeric Processor Extension They do not alter the
state of the 80C187 Numeric Processor Extension
(They are treated similarly to FNOP except that
ERROR is not checked ) While 8086 8087 code
containing these instructions can be executed on
the 80C186 80C187 it is unlikely that the exception-
handling routines containing these instructions will
be completely portable to the 80C187 Numeric Proc-
essor Extension
The 80C187 differs from the 8087 with respect to
instruction data and exception synchronization Ex-
cept for the processor control instructions all of the
80C187 numeric instructions are automatically syn-
chronized by the 80C186 CPU When necessary the
11
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| PDF Descargar | [ Datasheet 80C187.PDF ] | |
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