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PDF 80960MC Data sheet ( Hoja de datos )
| Número de pieza | 80960MC | |
| Descripción | EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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PRELIMINARY
80960MC
EMBEDDED 32-BIT MICROPROCESSOR
WITH INTEGRATED FLOATING-POINT UNIT
AND MEMORY MANAGEMENT UNIT
Commercial
s High-Performance Embedded Architecture s On-Chip Memory Management Unit
— 25 MIPS Burst Execution at 25 MHz
— 9.4 MIPS* Sustained Execution at
25 MHz
s On-Chip Floating Point Unit
— Supports IEEE 754 Floating Point
Standard
— 4 Gbyte Virtual Address Space per
Task
— 4 Kbyte Pages with Supervisor/User
Protection
s Built-in Interrupt Controller
— 32 Priority Levels
— Full Transcendental Support
— 248 Vectors
— Four 80-Bit Registers
— Supports M8259A
— 13.6 Million Whetstones/s
(Single Precision) at 25 MHz
s 512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached
Instructions
s Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored
On-Chip (Sixteen 32-Bit Registers per
Set)
— 3.4 µs Latency @ 25 MHz
s Easy to Use, High Bandwidth 32-Bit Bus
— 66.7 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
s Multitasking and Multiprocessor Support
— Automatic Task dispatching
— Prioritized Task Queues
s Advanced Package Technology
— 132-Lead Ceramic Pin Grid Array
— Register Scoreboarding
FOUR
80-BIT FP
REGISTERS
80-BIT
FPU
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
MMU
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BUS CONTROL
LOGIC
32-BIT
BURST
BUS
Figure 1. The 80960MC Processor’s Highly Parallel Architecture
© INTEL CORPORATION, 1997
September, 1997
Order Number: 273123-001
1 page  
80960MC
1.0 THE i960® MC PROCESSOR
The 80960MC, a member of Intel’s i960® 32-bit
processor family, is ideally suited for embedded
applications. It includes a 512-byte instruction cache
and a built-in interrupt controller. The 80960MC has
a large register set, multiple parallel execution units
and a high-bandwidth burst bus. Using advanced
RISC technology, this processor is capable of
execution rates in excess of 9.4 million instructions
per second*. The 80960MC is well-suited for a wide
range of applications including non-impact printers,
I/O control and specialty instrumentation. The
embedded market includes applications as diverse
as industrial automation, avionics, image
processing, graphics and networking. These types of
applications require high integration, low power
consumption, quick interrupt response times and
* Relative to Digital Equipment Corporation’s VAX-11/780*
at 1 MIPS
high performance. Since time to market is critical,
embedded processors must be easy to use in both
hardware and software designs.
All members of the i960 processor family share a
common core architecture which utilizes RISC tech-
nology so that, except for special functions, the
family members are object-code compatible. Each
new processor in the family adds its own special set
of functions to the core to satisfy the needs of a
specific application or range of applications in the
embedded market.
The 80960MC includes an integrated Floating Point
Unit (FPU), a Memory Management Unit (MMU),
multitasking support, and multiprocessor support.
Two commercial members of the i960® family
provide similar features: the 80960KB processor with
integrated FPU and the 80960KA without floating-
point.
0000 0000H
ADDRESS SPACE
FETCH
INSTRUCTION CACHE
INSTRUCTION
STREAM
FFFF FFFFH
ARCHITECTURALLY
DEFINED
DATA STRUCTURES
LOAD
STORE
INSTRUCTION
EXECUTION
PROCESSOR STATE
REGISTERS
INSTRUCTION
POINTER
ARITHMETIC
CONTROLS
PROCESS
CONTROLS
TRACE
CONTROLS
SIXTEEN 32-BIT GLOBAL REGISTERS
g0
g15
REGISTER CACHE
SIXTEEN 32-BIT LOCAL REGISTERS
r0
r15
FOUR 80-BIT FLOATING POINT REGISTERS
CONTROL REGISTERS
Figure 1. 80960MC Programming Environment
PRELIMINARY
1
5 Page 
80960MC
Table 3. Sample Floating-Point Execution Times
(µs) at 25 MHz
Function
Add
Subtract
Multiply
Divide
32-Bit
0.4
0.4
0.7
1.3
64-Bit
0.5
0.5
1.3
2.9
Square Root
Arctangent
Exponent
Sine
Cosine
3.7
10.1
11.3
15.2
15.2
3.9
13.1
12.5
16.6
16.6
1.1.9 Multitasking Support
Multitasking programs commonly involve the moni-
toring and control of an external operation, such as
the activities of a process controller or the move-
ments of a machine tool. These programs generally
consist of a number of processes that run indepen-
dently of one another, but share a common
database or pass data among themselves.
The 80960MC offers several hardware functions
designed to support multitasking systems. One
unique feature, called self-dispatching, allows a
processor to switch itself automatically among
scheduled tasks. When self-dispatching is used, all
the operating system is required to do is place the
task in the scheduling queue.
When the processor becomes available, it
dispatches the task from the beginning of the queue
and then executes it until it becomes blocked, inter-
rupted, or until its time-slice expires. It then returns
the task to the end of the queue (i.e., automatically
reschedules it) and dispatches the next ready task.
During these operations, no communication between
the processor and the operating system is necessary
until the running task is complete or an interrupt is
issued.
1.1.10 Synchronization and Communication
The 80960MC also offers instructions to set up and
test semaphores to ensure that concurrent tasks
remain synchronized and no data inconsistency
results. Special data structures, known as communi-
cation ports, provide the means for exchanging
parameters and data structures. Transmission of
PRELIMINARY
information by means of communication ports is
asynchronous and automatically buffered by the
processor.
Communication between tasks by means of ports
can be carried out independently of the operating
system. Once the ports have been set up by the
programmer, the processor handles the message
passing automatically.
1.1.11 High Bandwidth Local Bus
The 80960MC CPU resides on a high-bandwidth
address/data bus known as the local bus (L-Bus).
The L-Bus provides a direct communication path
between the processor and the memory and I/O
subsystem interfaces. The processor uses the L-Bus
to fetch instructions, manipulate memory and
respond to interrupts. L-Bus features include:
• 32-bit multiplexed address/data path
• Four-word burst capability which allows transfers
from 1 to 16 bytes at a time
• High bandwidth reads and writes with 66.7
MBytes/s burst (at 25 MHz)
• Special signal to indicate whether a memory trans-
action can be cached
Table 4 defines L-bus signal names and functions;
Table 5 defines other component-support signals
such as interrupt lines.
1.1.12 Multiple Processor Support
One means of increasing the processing power of a
system is to run two or more processors in parallel.
Since microprocessors are not generally designed to
run in tandem with other processors, designing such
a system is usually difficult and costly.
The 80960MC solves this problem by offering a
number of functions to coordinate the actions of
multiple processors. First, messages can be passed
between processors to initiate actions such as
flushing a cache, stopping or starting another
processor, or preempting a task. The messages are
passed on the bus and allow multiple processors to
run together smoothly, with rare need to lock the bus
or memory.
7
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