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PDF 80960KB Data sheet ( Hoja de datos )
| Número de pieza | 80960KB | |
| Descripción | EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT | |
| Fabricantes | Intel Corporation | |
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80960KB
EMBEDDED 32-BIT MICROPROCESSOR
WITH INTEGRATED FLOATING-POINT UNIT
s High-Performance Embedded Architecture
— 25 MIPS Burst Execution at 25 MHz
— 9.4 MIPS* Sustained Execution at 25 MHz
s 512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached Instruc-
tions
s Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored On-Chip
— Register Scoreboarding
s 4 Gigabyte, Linear Address Space
s Pin Compatible with 80960KA
s Built-in Interrupt Controller
— 31 Priority Levels, 256 Vectors
— 3.4 µs Latency @ 25 MHz
s Easy to Use, High Bandwidth 32-Bit Bus
— 66.7 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
s 132-Lead Packages:
— Pin Grid Array (PGA)
— Plastic Quad Flat-Pack (PQFP)
s On-Chip Floating Point Unit
— Supports IEEE 754 Floating Point Standard
— Four 80-Bit Registers
— 13.6 Million Whetstones/s (Single
Precision) at 25 MHz
The 80960KB is a member of Intel’s i960® 32-bit processor family, which is designed especially for embedded
applications. It includes a 512-byte instruction cache, an integrated floating-point unit and a built-in interrupt
controller. The 80960KB has a large register set, multiple parallel execution units and a high-bandwidth burst
bus. Using advanced RISC technology, this high performance processor is capable of execution rates in excess
of 9.4 million instructions per second*. The 80960KB is well-suited for a wide range of applications including non-
impact printers, I/O control and specialty instrumentation.
FOUR
80-BIT FP
REGISTERS
80-BIT
FPU
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BUS
CONTROL
LOGIC
32-BIT
BURST
BUS
Figure 1. The 80960KB Processor’s Highly Parallel Architecture
* Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment
Corporation)
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
May 1993
© INTEL CORPORATION, 1993
Order Number: 270565-006
1 page  
80960KB
Control
Opcode
Displacement
Compare and
Branch
Opcode Reg/Lit
Reg
M
Displacement
Register to
Register
Opcode Reg
Reg/Lit Modes
Ext’d Op
Reg/Lit
Memory Access—
Short
Opcode
Reg
Base M
X
Offset
Memory Access—
Long
Opcode
Reg
Base Mode
Displacement
Scale xx
Offset
Figure 3. Instruction Formats
1.1.1. Memory Space And Addressing Modes
The 80960KB offers a linear programming environ-
ment so that all programs running on the processor
are contained in a single address space. Maximum
address space size is 4 Gigabytes (232 bytes).
For ease of use the 80960KB has a small number of
addressing modes, but includes all those necessary
to ensure efficient execution of high-level languages
such as C. Table 2 lists the modes.
Table 2. Memory Addressing Modes
• 12-Bit Offset
• 32-Bit Offset
• Register-Indirect
• Register + 12-Bit Offset
• Register + 32-Bit Offset
• Register + (Index-Register x Scale-Factor)
• Register x Scale Factor + 32-Bit Displacement
• Register + (Index-Register x Scale-Factor) +
32-Bit Displacement
• Scale-Factor is 1, 2, 4, 8 or 16
1.1.2. Data Types
The 80960KB recognizes the following data types:
Numeric:
• 8-, 16-, 32- and 64-bit ordinals
• 8-, 16-, 32- and 64-bit integers
• 32-, 64- and 80-bit real numbers
Non-Numeric:
• Bit
• Bit Field
• Triple Word (96 bits)
• Quad-Word (128 bits)
1.1.3. Large Register Set
The 80960KB programming environment includes a
large number of registers. In fact, 32 registers are
available at any time. The availability of this many
registers greatly reduces the number of memory
accesses required to perform algorithms, which leads
to greater instruction processing speed.
There are two types of general-purpose registers:
local and global. The 20 global registers consist of
sixteen 32-bit registers (G0 though G15) and four
4
5 Page 
80960KB
Table 5. 80960KB Pin Description: Support Signals (Sheet 2 of 2)
NAME
TYPE
DESCRIPTION
FAILURE
O INITIALIZATION FAILURE indicates that the processor did not initialize correctly.
O.D. After RESET deasserts and before the first bus transaction begins, FAILURE asserts
while the processor performs a self-test. If the self-test completes successfully, then
FAILURE deasserts. The processor then performs a zero checksum on the first eight
words of memory. If it fails, FAILURE asserts for a second time and remains
asserted. If it passes, system initialization continues and FAILURE remains
deasserted.
IAC/INT0
I INTERAGENT COMMUNICATION REQUEST/INTERRUPT 0 indicates an IAC
message or an interrupt is pending. The bus interrupt control register determines how
the signal is interpreted. To signal an interrupt or IAC request in a synchronous
system, this pin — as well as the other interrupt pins — must be enabled by being
deasserted for at least one bus cycle and then asserted for at least one additional
bus cycle. In an asynchronous system the pin must remain deasserted for at least
two bus cycles and then asserted for at least two more bus cycles.
During system reset, this signal must be in the logic high condition to enable normal
processor operation. The logic low condition is reserved.
INT1
I INTERRUPT 1, like INT0, provides direct interrupt signaling.
INT2/INTR
I INTERRUPT2/INTERRUPT REQUEST: The interrupt control register determines
how this pin is interpreted. If INT2, it has the same interpretation as the INT0 and INT1
pins. If INTR, it is used to receive an interrupt request from an external interrupt
controller.
INT3/INTA
I/O INTERRUPT3/INTERRUPT ACKNOWLEDGE: The bus interrupt control register
O.D. determines how this pin is interpreted. If INT3, it has the same interpretation as the
INT0, INT1 and INT2 pins. If INTA, it is used as an output to control interrupt-
acknowledge transactions. The INTA output is latched on-chip and remains valid
during Td cycles; as an output, it is open-drain.
N.C.
N/A NOT CONNECTED indicates pins should not be connected. Never connect any pin
marked N.C. as these pins may be reserved for factory use.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
2.0 ELECTRICAL SPECIFICATIONS
2.1. Power and Grounding
The 80960KB is implemented in CHMOS IV
technology and therefore has modest power require-
ments. Its high clock frequency and numerous output
buffers (address/data, control, error and arbitration
signals) can cause power surges as multiple output
buffers simultaneously drive new signal levels. For
clean on-chip power distribution, VCC and VSS pins
separately feed the device’s functional units. Power
and ground connections must be made to all
80960KB power and ground pins. On the circuit
board, all Vcc pins must be strapped closely together,
preferably on a power plane; all Vss pins should be
strapped together, preferably on a ground plane.
2.2. Decoupling Recommendations
Place a liberal amount of decoupling capacitance
near the 80960KB. When driving the L-bus the
processor can cause transient power surges, particu-
larly when connected to a large capacitive load.
10
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