Datenblatt-pdf.com


80960JD-33 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer 80960JD-33
Beschreibung EMBEDDED 32-BIT MICROPROCESSOR
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
80960JD-33 Datasheet, Funktion
www.DataSheet4U.com
A
PRELIMINARY
80960JD
EMBEDDED 32-BIT MICROPROCESSOR
s Pin/Code Compatible with all 80960Jx
s High Bandwidth Burst Bus
Processors
— 32-Bit Multiplexed Address/Data
s High-Performance Embedded Architecture
— One Instruction/Clock Execution
— Core Clock Rate is 2x the Bus Clock
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
s New Instructions
— Conditional Add, Subtract and Select
— Processor Management
— User/Supervisor Protection Model
s High-Speed Interrupt Controller
s Two-Way Set Associative Instruction Cache — 31 Programmable Priorities
— 80960JD - 4 Kbyte
— Programmable Cache Locking
— Eight Maskable Pins plus NMI
— Up to 240 Vectors in Expanded Mode
Mechanism
s Two On-Chip Timers
s Direct Mapped Data Cache
— Independent 32-Bit Counting
— 80960JD - 2 Kbyte
— Write Through Operation
— Clock Prescaling by 1, 2, 4 or 8
— lnternal Interrupt Sources
s On-Chip Stack Frame Cache
— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
— 0-7 Frames Reserved for High-Priority
Interrupts
s On-Chip Data RAM
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
s Halt Mode for Low Power
s IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
s Packages
— 132-Lead Pin Grid Array (PGA)
— 132-Lead Plastic Quad Flat Pack (PQFP)
iA80960JD
XXXXXXXXA2
M © 19xx
PIN 1
132
33
A
i960®
iNG80960JD
XXXXXXXXA2
M © 19xx
99
66
Figure 1. 80960JD Microprocessor
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1995
September 1995
Order Number: 272596-002






80960JD-33 Datasheet, Funktion
www.DataSheet4U.com
80960JD
A
CLKIN
PLL, Clocks,
Power Mgmt
TAP Boundary Scan
5 Controller
8-Set
Local Register Cache
128
Global / Local
Register File
SRC1 SRC2 DEST
4 KByte Instruction Cache
Two-Way Set Associative
32-bit buses
address / data
Physical Region
Configuration
Bus
Control Unit
Bus Request
Queues
Control
21
Address/
Data Bus
32
Instruction Sequencer
Constants Control
Multiply
Divide
Unit
Execution
and
Address
Generation
Unit
effective
address
Memory
Interface
Unit
32-bit Address
32-bit Data
Two 32-Bit
Timers
Interrupt
Programmable Port
Interrupt Controller 9
Memory-Mapped
Register Interface
1 Kbyte
Data RAM
2 Kbyte Direct
Mapped Data
Cache
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
Figure 2. 80960JD Block Diagram
2.1 80960 Processor Core
The 80960Jx family is a scalar implementation of the
80960 Core Architecture. Intel designed this
processor core as a very high performance device
that is also cost-effective. Factors that contribute to
the core’s performance include:
• Core operates at twice the bus speed (80960JD
only)
• Single-clock execution of most instructions
• Independent Multiply/Divide Unit
• Efficient instruction pipeline minimizes pipeline
break latency
• Register and resource scoreboarding allow
overlapped instruction execution
• 128-bit register bus speeds local register caching
• 4 Kbyte two-way set associative, integrated
instruction cache
• 2 Kbyte direct-mapped, integrated data cache
• 1 Kbyte integrated data RAM delivers zero wait
state program data
2.2 Burst Bus
A 32-bit high-performance bus controller interfaces
the 80960JD to external memory and peripherals.
The BCU fetches instructions and transfers data at
the rate of up to four 32-bit words per six clock
cycles. The external address/data bus is multiplexed.
2 PRELIMINARY

6 Page









80960JD-33 pdf, datenblatt
www.DataSheet4U.com
80960JD
A
NAME
BE3:0
WIDTH/
HLTD1:0
D/C
W/R
Table 3. Pin Description — External Bus Signals (Sheet 2 of 4)
TYPE
O
R(1)
H(Z)
P(1)
O
R(0)
H(Z)
P(1)
O
R(X)
H(Z)
P(Q)
O
R(0)
H(Z)
P(Q)
DESCRIPTION
BYTE ENABLES select which of up to four data bytes on the bus participate in the
current bus access. Byte enable encoding is dependent on the bus width of the
memory region accessed:
32-bit bus:
BE3 enables data on AD31:24
BE2 enables data on AD23:16
BE1 enables data on AD15:8
BE0 enables data on AD7:0
16-bit bus:
BE3 becomes Byte High Enable (enables data on AD15:8)
BE2 is not used (state is high)
BE1 becomes Address Bit 1 (A1)
BE0 becomes Byte Low Enable (enables data on AD7:0)
8-bit bus:
BE3 is not used (state is high)
BE2 is not used (state is high)
BE1 becomes Address Bit 1 (A1)
BE0 becomes Address Bit 0 (A0)
The processor asserts byte enables, byte high enable and byte low enable during Ta.
Since unaligned bus requests are split into separate bus transactions, these signals
do not toggle during a burst. They remain active through the last Td cycle.
For accesses to 8- and 16-bit memory, the processor asserts the address bits in
conjunction with A3:2 described above.
WIDTH/HALTED signals denote the physical memory attributes for a bus transaction:
WIDTH/HLTD1
WIDTH/HLTD0
00
01
10
11
8 Bits Wide
16 Bits Wide
32 Bits Wide
Processor Halted
The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in
response to a HOLD request, regardless of prior operating state.
DATA/CODE indicates that a bus access is a data access (1) or an instruction access
(0). D/C has the same timing as W/R.
0 = instruction access
1 = data access
WRITE/READ specifies, during a Ta cycle, whether the operation is a write (1) or read
(0). It is latched on-chip and remains valid during Td cycles.
0 = read
1 = write
8 PRELIMINARY

12 Page





SeitenGesamt 30 Seiten
PDF Download[ 80960JD-33 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
80960JD-33EMBEDDED 32-BIT MICROPROCESSORIntel Corporation
Intel Corporation

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche