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PDF 80960CF-30 Data sheet ( Hoja de datos )
| Número de pieza | 80960CF-30 | |
| Descripción | SPECIAL ENVIRONMENT 80960CF-30/ -25/ -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR | |
| Fabricantes | Intel Corporation | |
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SPECIAL ENVIRONMENT 80960CF-30 -25 -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
PROCESSOR
Socket and Object Code Compatible with 80960CA
Two Instructions Clock Sustained Execution
Four 59 Mbytes s DMA Channels with Data Chaining
Demultiplexed 32-bit Burst Bus with Pipelining
Y 32-bit Parallel Architecture
Two Instructions clock Execution
Load Store Architecture
Sixteen 32-bit Global Registers
Sixteen 32-bit Local Registers
Manipulate 64-bit Bit Fields
11 Addressing Modes
Full Parallel Fault Model
Supervisor Protection Model
Y Fast Procedure Call Return Model
Full Procedure Call in 4 clocks
Y On-Chip Register Cache
Caches Registers on Call Ret
Minimum of 6 Frames provided
Up to 15 Programmable Frames
Y On-Chip Instruction Cache
4 Kbyte Two-Way Set Associative
128-bit Path to Instruction Sequencer
Cache-Lock Modes
Cache-Off Mode
Y On-Chip Data Cache
1 Kbyte Direct-Mapped
Write Through
128 bits per Clock Access on
Cache Hit
Y Product Grades Available
SE3 b40 C to a110 C
Y High Bandwidth On-Chip Data RAM
1 Kbytes On-Chip RAM for Data
Sustain 128 bits per clock access
Y Four On-Chip DMA Channels
59 Mbytes s Fly-by Transfers
32 Mbytes s Two-Cycle Transfers
Data Chaining
Data Packing Unpacking
Programmable Priority Method
Y 32-Bit Demultiplexed Burst Bus
128-bit Internal Data Paths to and
from Registers
Burst Bus for DRAM Interfacing
Address Pipelining Option
Fully Programmable Wait States
Supports 8 16 or 32-bit Bus Widths
Supports Unaligned Accesses
Supervisor Protection Pin
Y Selectable Big or Little Endian Byte
Ordering
Y High-Speed Interrupt Controller
Up to 248 External Interrupts
32 Fully Programmable Priorities
Multi-mode 8-bit Interrupt Port
Four Internal DMA Interrupts
Separate Non-maskable Interrupt Pin
Context Switch in 750 ns Typical
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
January 1995
Order Number 271328-001
1 page  
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SPECIAL ENVIRONMENT 80960CF-30 -25 -16
1 0 PURPOSE
This document previews electrical characterizations
of Intel’s i960 CF embedded microprocessor (avail-
able in 33 25 and 16 MHz) For a detailed descrip-
tion of any i960 CF processor functional topic oth-
er than parametric performance refer to the latest
i960 CA Microprocessor Reference Manual (Order
No 270710) and the i960 CF Reference Manual Ad-
dendum (Order No 272188)
2 0 i960 CF PROCESSOR OVERVIEW
Intel’s i960 CF microprocessor is the performance
follow-on product to the i960 CA processor The
i960 CF product is socket- and object code-compati-
ble with the CA this makes CA-to-CF design up-
grades straightforward The i960 CF processor’s in-
struction cache is 4 Kbytes (CA device has 1 Kbyte)
CF data cache is 1 Kbyte (CA device has no data
cache) This extra cache on the CF product adds a
significant performance boost over the CA The
80960CF is object code compatible with the 32-bit
80960 Core Architecture while including Special
Function Register extensions to control on-chip pe-
ripherals and instruction set extensions to shift 64-
bit operands and configure on-chip hardware Multi-
ple 128-bit internal busses on-chip instruction cach-
ing and a sophisticated instruction scheduler allow
the processor to sustain execution of two instruc-
tions every clock and peak at execution of three
instructions per clock
A 32-bit demultiplexed and pipelined burst bus pro-
vides a 132 Mbyte s bandwidth to a system’s high-
speed external memory sub-system In addition the
80960CF’s on-chip caching of instructions proce-
dure context and critical program data substantially
decouples system performance from the wait states
associated with accesses to the system’s slower
cost sensitive main memory sub-system
The 80960CF bus controller also integrates full wait
state and bus width control for highest system per-
formance with minimal system design complexity
Unaligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CF
The processor also integrates four complete data-
chaining DMA channels and a high-speed interrupt
controller on-chip The DMA channels perform sin-
gle-cycle or two-cycle transfers data packing and
unpacking and data chaining Block transfers in ad-
dition to source or destination synchronized trans-
fers are provided
The interrupt controller provides full programmability
of 248 interrupt sources into 32 priority levels with a
typical interrupt task switch (‘‘latency’’) time of
750 ns
Figure 2 80960CF Block Diagram
271328 – 2
5
5 Page 
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SPECIAL ENVIRONMENT 80960CF-30 -25 -16
Name
HOLDA
BREQ
DC
DMA
SUP
Table 2 80960CF Pin Description External Bus Signals (Continued)
Type
Description
O
S
H(1)
R(Q)
HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has
relinquished control of the external bus When HOLDA is asserted the external
address bus data bus and bus control signals are floated HOLD BOFF HOLDA
and BREQ are used together to arbitrate access to the processor’s external bus
by external bus agents Since the processor grants HOLD requests and enters the
Hold Acknowledge state even while RESET is asserted HOLDA pin state is
independent of the RESET pin
O
S
H(Q)
R(0)
BUS REQUEST is asserted when the bus controller has a request pending BREQ
can be used by external bus arbitration logic in conjunction with HOLD and
HOLDA to determine when to return mastership of the external bus to the
processor
O
S
H(Z)
R(Z)
DATA OR CODE is asserted for a data request and deasserted for instruction
requests D C has the same timing as W R
O
S
H(Z)
R(Z)
DMA ACCESS indicates whether the bus request was initiated by the DMA
controller DMA is asserted for any DMA request DMA is deasserted for all other
requests
O
S
H(Z)
R(Z)
SUPERVISOR ACCESS indicates whether the bus request is issued while in
supervisor mode SUP is asserted when the request has supervisor privileges and
is deasserted otherwise SUP can be used to isolate supervisor code and data
structures from non-supervisor requests
Name
RESET
FAIL
Type
I
A(L)
H(Z)
R(Z)
N(Z)
O
S
H(Q)
R(0)
Table 3 80960CF Pin Description Processor Control Signals
Description
RESET causes the chip to reset When RESET is asserted all external signals return
to the reset state When RESET is deasserted initialization begins When the 2-x clock
mode is selected RESET must remain asserted for 16 PCLK2 1 cycles before being
deasserted in order to guarantee correct processor initialization When the 1-x clock
mode is selected RESET must remain asserted for 10 000 PCLK2 1 cycles before
being deasserted in order to guarantee correct initialization The CLKMODE pin
selects 1-x or 2-x input clock division of the CLKIN pin
The processor’s Hold Acknowledge bus state functions while the chip is reset If the
processor’s bus is in the Hold Acknowledge state when RESET is asserted the
processor will internally reset but maintains the Hold Acknowledge state on external
pins until the Hold request is removed If a hold request is made while the processor is
in the reset state the processor bus grants HOLDA and enters the Hold Acknowledge
state
FAIL indicates failure of the processor’s self-test performed at initialization When
RESET is deasserted and the processor begins initialization the FAIL pin is asserted
An internal self-test is performed as part of the initialization process If this self-test
passes the FAIL pin is deasserted otherwise it remains asserted The FAIL pin is
reasserted while the processor performs an external bus self-confidence test If this
self-test passes the processor deasserts the FAIL pin and branches to the user’s
initialization routine otherwise the FAIL pin remains asserted Internal self-test and the
use of the FAIL pin can be disabled with the STEST pin
11
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