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80960CF-16 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer 80960CF-16
Beschreibung SPECIAL ENVIRONMENT 80960CF-30/ -25/ -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
80960CF-16 Datasheet, Funktion
A
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PRELIMINARY
80960CF-40, -33, -25, -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
EMBEDDED MICROPROCESSOR
• Socket and Object Code Compatible with 80960CA
• Two Instructions/Clock Sustained Execution
• Four 71 Mbytes/s DMA Channels with Data Chaining
• Demultiplexed 32-Bit Burst Bus with Pipelining
s 32-Bit Parallel Architecture
— Two Instructions/clock Execution
— Load/Store Architecture
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers
— Manipulates 64-Bit Bit Fields
— 11 Addressing Modes
— Full Parallel Fault Model
— Supervisor Protection Model
s Fast Procedure Call/Return Model
— Full Procedure Call in 4 Clocks
s On-Chip Register Cache
— Caches Registers on Call/Ret
— Minimum of 6 Frames Provided
— Up to 15 Programmable Frames
s On-Chip Instruction Cache
— 4 Kbyte Two-Way Set Associative
— 128-Bit Path to Instruction Sequencer
— Cache-Lock Modes
— Cache-Off Mode
s High Bandwidth On-Chip Data RAM
— 1 Kbyte On-Chip Data RAM
— Sustains 128 bits per Clock Access
s Selectable Big or Little Endian Byte
Ordering
s Four On-Chip DMA Channels
— 71 Mbytes/s Fly-by Transfers
— 40 Mbytes/s Two-Cycle Transfers
— Data Chaining
— Data Packing/Unpacking
— Programmable Priority Method
s 32-Bit Demultiplexed Burst Bus
— 128-Bit Internal Data Paths to and from
Registers
— Burst Bus for DRAM Interfacing
— Address Pipelining Option
— Fully Programmable Wait States
— Supports 8-, 16- or 32-Bit Bus Widths
— Supports Unaligned Accesses
— Supervisor Protection Pin
s High-Speed Interrupt Controller
— Up to 248 External Interrupts
— 32 Fully Programmable Priorities
— Multi-mode 8-Bit Interrupt Port
— Four Internal DMA Interrupts
— Separate, Non-maskable Interrupt Pin
— Context Switch in 625 ns Typical
s On-Chip Data Cache
— 1 Kbyte Direct-Mapped, Write Through
— 128 bits per Clock Access on Cache Hit
© INTEL CORPORATION, 1996
June 1996
Order Number: 272886-001






80960CF-16 Datasheet, Funktion
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80960CF-16 pdf, datenblatt
80960CF-40, -33, -25, -16
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A
Name
A31:2
D31:0
BE3:0
W/R
ADS
READY
6
Table 2. 80960CF Pin Description — External Bus Signals (Sheet 1 of 3)
Type
O
S
H(Z)
R(Z)
I/O
S(L)
H(Z)
R(Z)
O
S
H(Z)
R(1)
O
S
H(Z)
R(0)
O
S
H(Z)
R(1)
I
S(L)
H(Z)
R(Z)
Description
ADDRESS BUS carries the physical address’ upper 30 bits. A31 is the most significant
bit; A2 is least significant. During a bus access, A31:2 identify all external addresses to
word (4-byte) boundaries. Byte enable signals indicate the selected byte in each word.
During burst accesses, A3:2 increment to indicate successive data cycles.
DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configura-
tion. The least significant bit is carried on D0 and the most significant on D31. When the
bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used. For 16-bit data
bus widths, D15:0 are used. For 32-bit bus widths the full data bus is used.
BYTE ENABLES select which of the four bytes addressed by A31:2 are active during
an access to a memory region configured for a 32-bit data-bus width. BE3 applies to
D31:24; BE2 applies to D23:16; BE1 applies to D15:8 BE0 applies to D7:0.
32-bit bus:
BE3
Byte Enable 3
enable D31:24
BE2
Byte Enable 2
enable D23:16
BE1
Byte Enable 1
enable D15:8
BE0
Byte Enable 0
enable D7:0
For accesses to a memory region configured for a 16-bit data-bus width, the processor
uses the BE3, BE1 and BE0 pins as BHE, A1 and BLE respectively.
16-bit bus:
BE3 Byte High Enable (BHE) enable D15:8
BE2 Not used (driven high or low)
BE1 Address Bit 1 (A1)
BE0 Byte Low Enable (BLE) enable D7:0
For accesses to a memory region configured for an 8-bit data-bus width, the processor
uses the BE1 and BE0 pins as A1 and A0 respectively.
8-bit bus:
BE3 Not used (driven high or low)
BE2 Not used (driven high or low)
BE1 Address Bit 1 (A1)
BE0 Address Bit 0 (A0)
WRITE/READ is asserted for read requests and deasserted for write requests. The
W/R signal changes in the same clock cycle as ADS. It remains valid for the entire
access in non-pipelined regions. In pipelined regions, W/R is not guaranteed to be valid
in the last cycle of a read access.
ADDRESS STROBE indicates a valid address and the start of a new bus access. ADS
is asserted for the first clock of a bus access.
READY is an input which signals the termination of a data transfer. READY is used to
indicate that read data on the bus is valid or that a write-data transfer has completed.
The READY signal works in conjunction with the internally programmed wait-state
generator. If READY is enabled in a region, the pin is sampled after the programmed
number of wait-states has expired. If the READY pin is deasserted, wait states continue
to be inserted until READY becomes asserted. This is true for the NRAD, NRDD, NWAD
and NWDD wait states. The NXDA wait states cannot be extended.
PRELIMINARY

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