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PDF 7C199-35 Data sheet ( Hoja de datos )
| Número de pieza | 7C199-35 | |
| Descripción | 32K x 8 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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99
CY7C199
Features
• High speed
— 10 ns
• Fast tDOE
• CMOS for optimum speed/power
• Low active power
— 467 mW (max, 12 ns “L” version)
• Low standby power
www.DataSheet4U—.co0m.275 mW (max, “L” version)
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY7C199 is a high-performance CMOS static RAM orga-
nized as 32,768 words by 8 bits. Easy memory expansion is
32K x 8 Static RAM
provided by an active LOW Chip Enable (CE) and active LOW
Output Enable (OE) and three-state drivers. This device has
an automatic power-down feature, reducing the power con-
sumption by 81% when deselected. The CY7C199 is in the
standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O0
through I/O7) is written into the memory location addressed by
the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
Logic Block Diagram
A0
A1
A2
A3
A4
AA56
A7
A8
A9
CE
WE
OE
INPUT BUFFER
1024 x 32 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
Selection Guide
C199–1
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Pin Configurations
DIP / SOJ / SOIC
Top View
LCC
Top View
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 WE
26 A4
25 A3
24 A2
23 A1
22 OE
21 A0
20 CE
19 I/O7
18 I/O6
3 2 1 2827
A8 4
A9 5
A10 6
A11 7
A12 8
A13 9
A14 10
26 A4
25 A3
24 A2
23 A1
22 OE
21 A0
20 CE
I/O0 11
19 I/O7
I/O1 12
18 I/O6
1314151617
17 I/O5
C199–3
16 I/O4
15 I/O3
C199–2
OE
A1
A2
A3
A4
WE
V CC
A5
A6
A7
A8
A9
A 10
A 11
22
23
24
25
26
27
28
1
2
3
4
5
6
7
TSOP I
Top View
(not to scale)
21 A 0
20 CE
19 I/O 7
18 I/O 6
17 I/O 5
16 I/O 4
15 I/O 3
14 GND
13 I/O 2
12 I/O 1
11 I/O 0
10 A 14
9 A 13
8 A 12
C199–4
Maximum Access Time (ns)
Maximum Operating
Current (mA)
L
Maximum CMOS
Standby Current (mA) L
7C199-8
8
120
0.5
7C199-10
10
110
90
0.5
0.05
7C199-12
12
160
90
10
0.05
7C199-15
15
155
90
10
0.05
7C199-20
20
150
90
10
0.05
7C199-25
25
150
80
10
0.05
7C199-35
35
140
70
10
0.05
7C199-45
45
140
10
Shaded area contains advance information.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05160 Rev. **
Revised September 7, 2001
1 page  
CY7C199
Switching Characteristics Over the Operating Range[3, 7]
7C199-8
7C199-10
7C199-12
7C199-15
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time
tAA Address to Data Valid
tOHA
Data Hold from Address Change
tACE CE LOW to Data Valid
www.DataSheett4DUO.Ecom
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[8]
OE HIGH to High Z[8, 9]
CE LOW to Low Z[8]
CE HIGH to High Z[8,9]
tPU CE LOW to Power-Up
tPD CE HIGH to Power-Down
WRITE CYCLE[10, 11]
8 10 12 15
8 10 12 15
3333
8 10 12 15
4.5 5 5 7
0000
5557
3333
4557
0000
8 10 12 15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC Write Cycle Time
tSCE CE LOW to Write End
tAW Address Set-Up to Write End
tHA Address Hold from Write End
tSA Address Set-Up to Write Start
tPWE
WE Pulse Width
tSD Data Set-Up to Write End
tHD
tHZWE
tLZWE
Data Hold from Write End
WE LOW to High Z[9]
WE HIGH to Low Z[8]
Shaded area contains advance information.
8 10 12 15 ns
7 7 9 10 ns
7 7 9 10 ns
0 0 0 0 ns
0 0 0 0 ns
7 7 8 9 ns
5 5 8 9 ns
0 0 0 0 ns
5 6 7 7 ns
3 3 3 3 ns
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05160 Rev. **
Page 5 of 16
5 Page 
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
VOL
VIH
VIL Max.
IIX
IOZ
www.DataSheet4U.cIoCmC
ISB1
ISB2
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Switching Characteristics
Parameter
READ CYCLE
tRC
tAA
tOHA
tACE
tDOE
WRITE CYCLE
tWC
tAA
tAW
tHA
tSA
tPWE
tSD
tHD
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
CY7C199
Document #: 38-05160 Rev. **
Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet 7C199-35.PDF ] | |
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