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89C51 Schematic ( PDF Datasheet ) - ATMEL Corporation

Teilenummer 89C51
Beschreibung 8 Bit Microcontroller with 4 Kbytes Flash
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 




Gesamt 15 Seiten
89C51 Datasheet, Funktion
Features
Compatible with MCS-51Products
4 Kbytes of In-System Reprogrammable Flash Memory
Endurance: 1,000 Write/Erase Cycles
Fully Static Operation: 0 Hz to 24 MHz
Three-Level Program Memory Lock
128 x 8-Bit Internal RAM
32 Programmable I/O Lines
Two 16-Bit Timer/Counters
Six Interrupt Sources
Programmable Serial Channel
•• Low Power Idle and Power Down Modes
Description
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4
Kbytes of Flash Programmable and Erasable Read Only Memory (PEROM). The
device is manufactured using Atmel’s high density nonvolatile memory technology
and is compatible with the industry standard MCS-51instruction set and pinout.
The on-chip Flash allows the program memory to be reprogrammed in-system or by
a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU
with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer
which provides a highly flexible and cost effective solution to many embedded control
applications.
Pin Configurations
(continued)
PDIP/Cerdip
INDEX
CORNER
P1.5
P1.6
P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
PQFP/TQFP
4 44 34 24 14 03 93 83 73 63 53 4
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
1
21
31
41
51
61
71
1
8
9
2
0
2
12
2
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
X TA L 2
X TA L 1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 P0.0 (AD0)
38 P0.1 (AD1)
37 P0.2 (AD2)
36 P0.3 (AD3)
35 P0.4 (AD4)
34 P0.5 (AD5)
33 P0.6 (AD6)
32 P0.7 (AD7)
31 EA/VPP
30 ALE/PROG
29 PSEN
28 P2.7 (A15)
27 P2.6 (A14)
26 P2.5 (A13)
25 P2.4 (A12)
24 P2.3 (A11)
23 P2.2 (A10)
22 P2.1 (A9)
21 P2.0 (A8)
PLCC/LCC
INDEX
CORNER
P1.5
P1.6
P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
6 4 2 44 42 40
7 5 3 1 43 4139
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
11781 92 02 12 22 32 42 52 62 72289
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
8-Bit
Microcontroller
with 4 Kbytes
Flash
AT89C51
0265E






89C51 Datasheet, Funktion
Programming the Flash (Continued)
tempted read of the last byte written will result in the com-
plement of the written datum on PO.7. Once the write cy-
cle has been completed, true data are valid on all outputs,
and the next cycle may begin. Data Polling may begin any
time after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can
also be monitored by the RDY/BSY output signal. P3.4 is
pulled low after ALE goes high during programming to in-
dicate BUSY. P3.4 is pulled high again when program-
ming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been
programmed, the programmed code data can be read
back via the address and data lines for verification. The
lock bits cannot be verified directly. Verification of the lock
bits is achieved by observing that their features are en-
abled.
Chip Erase: The entire Flash array is erased electrically
by using the proper combination of control signals and by
holding ALE/PROG low for 10 ms. The code array is writ-
ten with all “1"s. The chip erase operation must be exe-
cuted before the code memory can be re-programmed.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 030H,
031H, and 032H, except that P3.6 and P3.7 must be
pulled to a logic low. The values returned are as follows.
(030H) = 1EH indicates manufactured by Atmel
(031H) = 51H indicates 89C51
(032H) = FFH indicates 12 V programming
(032H) = 05H indicates 5 V programming
Programming Interface
Every code byte in the Flash array can be written and the
entire array can be erased by using the appropriate com-
bination of control signals. The write operation cycle is
self-timed and once initiated, will automatically time itself
to completion.
All major programming vendors offer worldwide support
for the Atmel microcontroller series. Please contact your
local programming vendor for the appropriate software re-
vision.
Flash Programming Modes
Mode
RST
ALE/
PSEN PROG
EA/
VPP P2.6 P2.7 P3.6 P3.7
Write Code Data
HL
H/12V(1)
L
H
H
H
Read Code Data
H LH
HL LHH
Write Lock
Bit - 1
H
L
H/12V
H
H
H
H
Bit - 2
H
L
(2) H/12V
H
H
L
L
Bit - 3
H
L
H/12V
H
L
H
L
Chip Erase
HL
Read Signature
Byte
H LH
Notes: 1. The signature byte at location 032H designates
whether VPP = 12 V or VPP = 5 V should be used to
enable programming.
H/12V
H
L
L
HL L L
2. Chip Erase requires a 10 ms PROG pulse.
L
L
6 AT89C51

6 Page









89C51 pdf, datenblatt
External Data Memory Cycle
ALE
tLHLL
PSEN
WR
PORT 0
PORT 2
tLLWL
tWLWH
tAVLL
tLLAX
tQVWX
A0 - A7 FROM RI OR DPL
tAVWL
tQVWH
DATA OUT
P2.0 - P2.7 OR A8 - A15 FROM DPH
tWHLH
tWHQX
A0 - A7 FROM PCL INSTR IN
A8 - A15 FROM PCH
External Clock Drive Waveforms
VCC - 0.5V
tCHCX
0.7 VCC
0.45V
0.2 VCC - 0.1V
tCLCH
tCHCX
tCLCX
tCLCL
tCHCL
External Clock Drive
Symbol
1/tCLCL
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
Parameter
Oscillator Frequency
Clock Period
High Time
Low Time
Rise Time
Fall Time
Min
0
41.6
15
15
Max
24
20
20
Units
MHz
ns
ns
ns
ns
ns
12 AT89C51

12 Page





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