Datenblatt-pdf.com


PERICOMPI7C8150 Schematic ( PDF Datasheet ) - Pericom Semiconductor Corporation

Teilenummer PERICOMPI7C8150
Beschreibung 2-Port PCI-to-PCI Bridge
Hersteller Pericom Semiconductor Corporation
Logo Pericom Semiconductor Corporation Logo 




Gesamt 70 Seiten
PERICOMPI7C8150 Datasheet, Funktion
PI7C8150
2-Port PCI-to-PCI Bridge
REVISION 1.02
2380 Bering Drive, San Jose, CA 95131
Telephone: 1-877-PERICOM, (1-877-737-4266)
Fax: 408-435-1100
Internet: http://www.pericom.com






PERICOMPI7C8150 Datasheet, Funktion
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
13 SUPPORTED COMMANDS......................................................................................................... 60
13.1 PRIMARY INTERFACE ............................................................................................................. 60
13.2 SECONDARY INTERFACE ....................................................................................................... 61
14 CONFIGURATION REGISTERS................................................................................................ 62
14.1 CONFIGURATION REGISTER ................................................................................................. 62
14.1.1 VENDOR ID REGISTER – OFFSET 00h......................................................................... 63
14.1.2 DEVICE ID REGISTER – OFFSET 00h .......................................................................... 63
14.1.3 COMMAND REGISTER – OFFSET 04h.......................................................................... 63
14.1.4 STATUS REGISTER – OFFSET 04h ................................................................................ 64
14.1.5 REVISION ID REGISTER – OFFSET 08h ...................................................................... 65
14.1.6 CLASS CODE REGISTER – OFFSET 08h....................................................................... 65
14.1.7 CACHE LINE SIZE REGISTER – OFFSET 0Ch ............................................................ 65
14.1.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ........................................... 66
14.1.9 HEADER TYPE REGISTER – OFFSET 0Ch................................................................... 66
14.1.10 PRIMARY BUS NUMBER REGISTSER – OFFSET 18h............................................ 66
14.1.11 SECONDARY BUS NUMBER REGISTER – OFFSET 18h ........................................ 66
14.1.12 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h.................................... 66
14.1.13 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h .................................. 66
14.1.14 I/O BASE REGISTER – OFFSET 1Ch.......................................................................... 67
14.1.15 I/O LIMIT REGISTER – OFFSET 1Ch ........................................................................ 67
14.1.16 SECONDARY STATUS REGISTER – OFFSET 1Ch................................................... 67
14.1.17 MEMORY BASE REGISTER – OFFSET 20h .............................................................. 68
14.1.18 MEMORY LIMIT REGISTER – OFFSET 20h............................................................. 68
14.1.19 PEFETCHABLE MEMORY BASE REGISTER – OFFSET 24h ................................ 68
14.1.20 PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h ............................ 69
14.1.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER –
OFFSET 28h ....................................................................................................................................... 69
14.1.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER –
OFFSET 2Ch....................................................................................................................................... 69
14.1.23 I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .......................... 69
14.1.24 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h......................... 70
14.1.25 ECP POINTER REGISTER – OFFSET 34h................................................................. 70
14.1.26 INTERRUPT LINE REGISTER – OFFSET 3Ch ......................................................... 70
14.1.27 INTERRUPT PIN REGISTER – OFFSET 3Ch............................................................ 70
14.1.28 BRIDGE CONTROL REGISTER – OFFSET 3Ch ....................................................... 70
14.1.29 DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h.................................. 71
14.1.30 ARBITER CONTROL REGISTER – OFFSET 40h ...................................................... 72
14.1.31 EXTENDED CHIP CONTROL REGISTER – OFFSET 48h....................................... 73
14.1.32 UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h ............................... 73
14.1.33 SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET
4Ch .......................................................................................................................................... 73
14.1.34 UPSTREAM (S TO P) MEMORY BASE REGISTER – OFFSET 50h ........................ 74
14.1.35 UPSTREAM (S TO P) MEMORY LIMIT REGISTER – OFFSET 50h....................... 74
14.1.36 UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER – OFFSET 54h
.......................................................................................................................................... 74
14.1.37 UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS REGISTER – OFFSET
58h .......................................................................................................................................... 75
14.1.38 P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h........................................ 75
14.1.39 GPIO DATA AND CONTROL REGISTER – OFFSET 64h ........................................ 76
14.1.40 SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h ................................. 76
14.1.41 P_SERR_L STATUS REGISTER – OFFSET 68h ........................................................ 77
14.1.42 PORT OPTION REGISTER – OFFSET 74h................................................................. 77
vi
August 22, 2002 – Revision 1.02

6 Page









PERICOMPI7C8150 pdf, datenblatt
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
2
2.1
2.2
2.2.1
SIGNAL DEFINITIONS
Signal Types
Signal Type
I
O
P
TS
STS
OD
Description
Input Only
Output Only
Power
Tri-State bi-directional
Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when
deasserting.
Open Drain
Signals
Note: Signal names that end with “_L” are active LOW.
PRIMARY BUS INTERFACE SIGNALS
Name
P_AD[31:0]
P_CBE[3:0]
P_PAR
P_FRAME_L
Pin #
49, 50, 55, 57, 58,
60, 61, 63, 67, 68,
70, 71, 73, 74, 76,
77, 93, 95, 96, 98,
99, 101, 107, 109,
112, 113, 115,
116, 118, 119,
121, 122
64, 79, 92, 110
90
80
Type
TS
TS
TS
STS
Description
Primary Address / Data: Multiplexed address and data
bus. Address is indicated by P_FRAME_L assertion.
Write data is stable and valid when P_IRDY_L is
asserted and read data is stable and valid when
P_TRDY_L is asserted. Data is transferred on rising
clock edges when both P_IRDY_L and P_TRDY_L are
asserted. During bus idle, PI7C8150 drives P_AD to a
valid logic level when P_GNT_L is asserted.
Primary Command/Byte Enables: Multiplexed
command field and byte enable field. During address
phase, the initiator drives the transaction type on these
pins. After that, the initiator drives the byte enables
during data phases. During bus idle, PI7C8150 drives
P_CBE[3:0] to a valid logic level when P_GNT_L is
asserted.
Primary Parity. Parity is even across P_AD[31:0],
P_CBE[3:0], and P_PAR (i.e. an even number of 1’s).
P_PAR is an input and is valid and stable one cycle after
the address phase (indicated by assertion of
P_FRAME_L) for address parity. For write data phases,
P_PAR is an input and is valid one clock after
P_IRDY_L is asserted. For read data phase, P_PAR is
an output and is valid one clock after P_TRDY_L is
asserted. Signal P_PAR is tri-stated one cycle after the
P_AD lines are tri-stated. During bus idle, PI7C8150
drives P_PAR to a valid logic level when P_GNT_L is
asserted.
Primary FRAME (Active LOW). Driven by the
initiator of a transaction to indicate the beginning and
duration of an access. The de-assertion of P_FRAME_L
indicates the final data phase requested by the initiator.
Before being tri-stated, it is driven to a de-asserted state
for one cycle.
2
August 22, 2002 – Revision 1.02

12 Page





SeitenGesamt 70 Seiten
PDF Download[ PERICOMPI7C8150 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
PERICOMPI7C81502-Port PCI-to-PCI BridgePericom Semiconductor Corporation
Pericom Semiconductor Corporation

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche