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Teilenummer | PEF20550 |
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Beschreibung | ICs for Communications | |
Hersteller | Infineon Technologies AG | |
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Gesamt 30 Seiten www.DataSheet4U.com
ICs for Communications
Extended Line Card Interface Controller
ELIC®
PEB 20550
PEF 20550
Versions 1.3
User’s Manual 01.96
T2055-0V13-M1-7600
PEB 20550
Table of Contents
Page
3.8.6.4 PCM- and CFI-Interface Activation Example . . . . . . . . . . . . . . . . . . . . . .117
3.8.6.5 SACCO-B Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
4
4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.5
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.6.7
4.6.8
4.6.9
4.6.10
4.6.11
4.6.12
4.6.13
4.6.14
4.6.15
4.6.16
4.6.17
4.6.18
4.6.19
4.6.20
4.6.21
4.6.22
4.6.23
4.6.24
4.6.25
4.6.26
4.6.27
Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Register Address Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Interrupt Top Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Interrupt Status Register (ISTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
PORT0 Data Register (PORT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
PORT1 Data Register (PORT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Port1 Configuration Register (PCON1) . . . . . . . . . . . . . . . . . . . . . . . . . .127
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Watchdog Control Register (WTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
ELIC® Mode Register / Version Number Register (EMOD) . . . . . . . . . .128
EPIC®-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
PCM-Mode Register (PMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Bit Number per PCM-Frame (PBNR) . . . . . . . . . . . . . . . . . . . . . . . . . . .132
PCM-Offset Downstream Register (POFD) . . . . . . . . . . . . . . . . . . . . . . .132
PCM-Offset Upstream Register (POFU) . . . . . . . . . . . . . . . . . . . . . . . . .133
PCM-Clock Shift Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
PCM-Input Comparison Mismatch (PICM) . . . . . . . . . . . . . . . . . . . . . . .135
Configurable Interface Mode Register 1 (CMD1) . . . . . . . . . . . . . . . . . .136
Configurable Interface Mode Register 2 (CMD2) . . . . . . . . . . . . . . . . . .138
Configurable Interface Bit Number Register (CBNR) . . . . . . . . . . . . . . .141
Configurable Interface Time Slot Adjustment Register (CTAR) . . . . . . .141
Configurable Interface Bit Shift Register (CBSR) . . . . . . . . . . . . . . . . . .142
Configurable Interface Subchannel Register (CSCR) . . . . . . . . . . . . . . .143
Memory Access Control Register (MACR) . . . . . . . . . . . . . . . . . . . . . . .144
Memory Access Address Register (MAAR) . . . . . . . . . . . . . . . . . . . . . . .147
Memory Access Data Register (MADR) . . . . . . . . . . . . . . . . . . . . . . . . .148
Synchronous Transfer Data Register (STDA) . . . . . . . . . . . . . . . . . . . . .148
Synchronous Transfer Data Register B (STDB) . . . . . . . . . . . . . . . . . . .149
Synchronous Transfer Receive Address Register A (SARA) . . . . . . . . .149
Synchronous Transfer Receive Address Register B (SARB) . . . . . . . . .150
Synchronous Transfer Transmit Address Register A (SAXA) . . . . . . . . .150
Synchronous Transfer Transmit Address Register B (SAXB) . . . . . . . . .151
Synchronous Transfer Control Register (STCR) . . . . . . . . . . . . . . . . . . .151
MF-Channel Active Indication Register (MFAIR) . . . . . . . . . . . . . . . . . . .152
MF-Channel Subscriber Address Register (MFSAR) . . . . . . . . . . . . . . .153
Monitor/Feature Control Channel FIFO (MFFIFO) . . . . . . . . . . . . . . . . .153
Signaling FIFO (CIFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Timer Register (TIMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Semiconductor Group
6
01.96
6 Page PEB 20550
PEF 20550
Overview
TE 0
8xS
TE 7
TE 0
8 x UPN
TE 7
TE 1
16 x t/r
TE 16
IOM R -2
2048 kbit/s
CFI PCM
S0
QUAT-S
PEB 2084
00
ELIC R
PEB 20550
U PN
OCTAT R -P
PEB 2096
1
SLIC
r/t
SICOFI R -4
PEB 2465
SLIC
TSS
Memory
D Arbiter
2
SACCO-A
3
SACCO-B
IOM R -2
PCM
Signaling
QUAT-S
PEB 2084
8xT
0
CO
7
µP Interface
µP IOM R -2 4 x D Cannel IDEC R
PEB 2075
ITB05392
Figure 1
Example for an Integrated Analog / Digital PBX
Semiconductor Group
12
01.96
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ PEF20550 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
PEF2055 | (PEF2054 / PEF2055) ICs for Communications | Siemens Semiconductor |
PEF20550 | ICs for Communications | Infineon Technologies AG |
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