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PEEL22CV10AZSI-25 Schematic ( PDF Datasheet ) - ETC

Teilenummer PEEL22CV10AZSI-25
Beschreibung CMOS Programmable Electrically Erasable Logic Device
Hersteller ETC
Logo ETC Logo 




Gesamt 10 Seiten
PEEL22CV10AZSI-25 Datasheet, Funktion
PEEL™ 22CV10AZ-25
CMOS Programmable Electrically Erasable Logic Device
Features
Ultra Low Power Operation
- VCC = 5 Volts ±10%
- Icc = 10 µA (typical) at standby
- Icc = 2 mA (typical) at 1 MHz
- tPD = 25ns.
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Development/Programmer Support
- Third party software and programmers
- Anachip PLACE Development Software
Architectural Flexibility
- 133 product terms x 44 input AND array
- Up to 22 inputs and 10 I/O pins
- 12 possible macrocell configurations
- Synchronous preset, asynchronous clear
- Independent output enables
- Programmable clock source and polarity
- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC
Application Versatility
- Replaces random logic
- Pin and JEDEC compatible with 22V10
- Ideal for power-sensitive systems
General Description
The PEEL™22CV10AZ is a Programmable Electrically Erasable
Logic (PEEL™) device that provides a low power alternative to
ordinary PLDs. The PEEL™22CV10AZ is available in 24-pin
DIP, SOIC, TSSOP and 28-pin PLCC packages (see Figure 19). A
“zero-power” (100µA max. ICC) standby mode makes the
PEEL™22CV10AZ ideal for power sensitive applications such as
handheld meters, portable communication equipment and lap- top
computers/ peripherals. EE-reprogrammability provides the
convenience of instant reprogramming for development and a
reusable production inventory minimizing the impact of pro-
gramming changes or errors. EE-reprogrammability also
improves factory testability, thus ensuring the highest quality
possible.
Figure 19 Pin Configuration
DIP
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
TSSOP
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I
The PEEL™22CV10AZ is JEDEC file compatible with standard
22V10 PLDs. Eight additional configurations per macrocell (a
total of 12) are also available by using the “+” software/program-
ming option (i.e., 22CV10AZ+ & 22CV10AZ++). The additional
macrocell configurations allow more logic to be put into every
device, potentially reducing the design's component count and
lowering the power requirements even further.
Development and programming support for the
PEEL™22CV10AZ is provided by popular third-party program-
mers and development software. Anachip also offers free Win-
PLACE development software.
Figure 19 Block Diagram
PLCC
SOIC
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
1/10






PEEL22CV10AZSI-25 Datasheet, Funktion
Zero Power Feature
The CMOS PEEL™22CV10AZ features “Zero-Power” standby
operation for ultra-low power consumption. With the “Zero-
Power” feature, transition-detection circuitry monitors the inputs,
I/Os (including CLK) and feedbacks. If these signals do not
change for a period of time greater than approximately two tPDs,
the outputs are latched in their current state and the device auto-
matically powers down. When the next signal transition is
detected, the device will “wake up” for active operation until the
signals stop switching long enough to trigger the next power-
down.
As a result of the “Zero-Power” feature, significant power sav-
ings can be realized for combinatorial or sequential operations
when the inputs or clock change at a modest rate (see Figure 23).
Figure 23 Typical ICC vs. Input Clock Frequency
for the 22CV10AZ.
22CV10AZ Frequency vs. ICC
100
10
1
0.1
Design Security
The PEEL™22CV10AZ provides a special EEPROM security bit
that prevents unauthorized reading or copying of designs pro-
grammed into the device. The security bit is set by the PLD pro-
grammer, either at the conclusion of the programming cycle or as a
separate step, after the device has been programmed. Once the
security bit is set it is impossible to verify (read) or program the
PEEL™ until the entire device has first been erased with the
bulk-erase function.
Signature Word
The signature word feature allows a 64-bit code to be pro-
grammed into the PEEL™22CV10AZ if the
PEEL™22CV10AZ+ software option is used. The code can be
read back even after the security bit has been set. The signature
word can be used to identify the pattern programmed into the
device or to record the design revision, etc.
Programming Support
Anachip’s JEDEC file translator allows easy conversion of exist-
ing 24 pin PLD designs to the PEEL™22CV10AZ, without the
need for redesign. Anachip supports a broad range of popular
third party design entry systems, including the Abel-to-PEEL
Arrays fitter software. Anachip also offers (for free) its propri-
etary WinPLACE software, an easy-to-use entry level PC-based
software development system.
Programming support includes all the popular third party pro-
grammers such as BP Microsystems, System General, Logical
Devices, and numerous others.
0.01
0.001
0.001
0.01
0.1
1
Frequency in MHz
10
Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Dec 16, 2004
6/10

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