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PDF PEB22622F Data sheet ( Hoja de datos )

Número de pieza PEB22622F
Descripción SDSL One Chip Rate Adaptive Transceiver with Embedded Start-up
Fabricantes Infineon Technologies AG 
Logotipo Infineon Technologies AG Logotipo



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PRODUCT BRIEF
SDSL One Chip Rate Adaptive
Transceiver with Embedded
Start-up
The one chip transceiver IC SOCRATESTM inte-
grates all functions of a SDSL transceiver accord-
ing to the emerging ETSI and ITU standards. It can
operate at all data rates from 144 kBit/s up to
2.3 MBit/s in 8 kBit/s granularity. Its small package
and low power consumption make it especially
useful in linecard and remote feed applications.
The integrated microcontroller and HDLC control-
ler make it easy to use in a variety of applications.
The built-in 2B1Q mode keeps it interoperable
with HDSL solutions. All features required for
operation in WLL/RITL systems are available. The
device is also interoperable with the MuBIC MDSL
chip. Infineon also supplies a wide range of other
telecom ICs to offer complete system solutions
for different applications.
Potential Applications
 High speed subscriber access
 N-channel DAML systems
 Extended range full and
fractional T1/E1
 Internet connections
 ISDN H0 transport
 ISDN Primary rate access
replacement
 Remote LAN Access (Home
office)
 Videoconferencing
 Cellular base stations
 RITL and WLL systems
 SDH and SONET termination
 Leased line services
 Frame Relay services
 PBX trunk lines
Features
 Single chip SDSL transceiver
 Plastic TQFP-144 package
 Lowest power consumption
 TCPAM linecode with 2, 3 or 4
Bits/symbol
 Synchronous or plesiochronous
operation
 8-Bit µC parallel interface of
Infineon/Intel and Motorola
multiplexed/demuliplexed type
 Transparent transmission or
built-in Framer with MuBIC or
SDSL framing
 Embedded µC also usable for
board control
 Two integrated HDLC control-
lers for payload and EOC
 Warmstart capability
 G. handshake start-up
SDSL
 Central office (COT) and
remote (RT) operation (master/
slave)
 2 MBit/s and 4 MBit/s TDM
interface in RT mode
 2 MBit/s to 10 MBit/s TDM inter-
face in COT mode
 1544 kBits/s TDM interface (T1)
 DECT base station synchroni-
zation
 Delay measurement
 2B1Q mode
 Single 2.0 V, 3.3 V and +5 V
power supply
 Inputs and Outputs TTL level
 Capable of transmitting on ETSI
and ANSI HDSL testloops
 JTAG boundary scan
Development and Support Tools
 SMART 2000 Evaluation
package
S O C R AT E S
PEB 22622
Never stop thinking.

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